A multi-mode display and control system of infrared remote control color lamp based on field programmable logic device (FPGA) is designed. It has the advantages of low cost, reliable performance and good expansibility. The circuit structure of the system is introduced in detail, and a construction method of infrared remote control system is proposed, which uses SC9148B infrared transmitter chip and peripheral circuit as transmitter, HS0038B infrared integrated chip as receiver, and FPGA as core controller. The system is validated by timing simulation and logic verification of FPGA. The results show that the design can well realize the functions of decoding control, key signal storage and decoding, and multi-mode display of color lamp infrared remote control signal.
With the rapid development of modern electronic technology, traditional design methods are gradually withdrawing from the historical stage. The chip design technology based on programmable logic device (FPGA) has gradually become the mainstream of electronic system design. The signal decoding of the traditional infrared remote control color lamp control system is mostly realized by single chip computer or ARM. The design of its encoder and decoder is software mode. In practical application, it is easy to be disturbed by the outside world and the program runs away. Moreover, the software decodes into serial operation, which has slow response speed, more CPU resources and low system reliability. In contrast, the parallel processing-based FPGA has remarkable advantages, such as high speed, high system integration, strong anti-interference ability, stable and reliable operation, and convenient design changes. In this paper, the infrared remote control of color lamp is realized by using the market mainstream FPGA technology, which fully integrates the communication technology, digital logic processing technology and the integrated application of the FPGA technology in engineering practice. Infrared remote control system generally consists of infrared transmitter, infrared receiver, core decoding microcontroller and its peripheral circuit. In this design, in the range of tens of meters, when the key is pressed, the infrared transmitter generates the control signal corresponding to the command/key, and identifies/encodes the control signal. After modulation, the serial data is sent out in the form of infrared light through the infrared transmitter.
The receiver receives the infrared signal from the transmitter, and detects, amplifies, filters, demodulates and shapes the received signal. Finally, the baseband signal is recovered from the carrier. The restored baseband signal is fed into the core decoding controller FPGA and converted into the corresponding control signal to complete the color lamp control. The transmitting circuit uses SC9148B as the main chip, and its modulation mode uses Pulse Position Modulation (PPM), which encodes remote control instructions into pulse sequence [4]. The `1’of the remote control command is expressed as a positive pulse with duty cycle [34], `0′ is expressed as a positive pulse with duty cycle [14], [a = 16 (38 kHz). The pulse position modulation coding method is shown in Figure 1. The encoding protocol consists of 12-bit key codes, each of which is composed of `0’and `1′ represented by the above encoding rules, and the length of time is [12*4a=48a]. ] When the key is pressed, the transmitting circuit will send two codes in a group of 12-bit codes (48a). Among them, the 60A time interval is the delay time from pressing the key to sending the code, the 80A time interval for sending 12-bit codes (48a) again, and the 208a time interval for sending two codes again.
The encoding instructions are sent continuously in the format shown in Figure 2. The working principle of the circuit is that when the key press is detected, the DOUT port outputs a 38 kHz high frequency modulation signal, which is amplified by the infrared emission driving circuit and sent out through the infrared emission tube. The general infrared receiver HS0038B is used to receive, amplify, filter and demodulate the infrared light signal. The demodulated logic level signal is sent to the FPGA through the extended I/O port. The decoding function of the received signal and the corresponding control of the color lamp mode are realized by the programming of the FPGA, thus the infrared remote control function of multi-mode display of the color lamp is realized. When designing the decoder, it should be noted that the HS0038B integrates inverters to ensure that the receiver has sufficient sensitivity.
The baseband signal recovered from the carrier is inverted from the baseband signal before the original modulation is transmitted. The core idea of the decoding controller of the FPGA is that according to the infrared communication protocol designed, the time length of the bit code `1’or `0′ in the 12-bit data transmission command is [4a,] this design will sample every bit of code in every [4a] time with high-level pulse [6?7]. In order to calculate the number of sampling pulses conveniently and minimize the error, the sampling clock frequency is 50 MHz. If the number of pulses obtained after sampling exceeds 10,000 and less than 30,000, it is judged as logical `1′; if the number of pulses obtained exceeds 30,000 and less than 80,000, it is judged as logical `0′; if the number of pulses does not meet the conditions, it is considered invalid. The calculation process of the global clock pulse sampling number is as follows: The decoding controller workflow chart is shown in Figure 4. The system is reset to the initial state.
First, the upper edge of the input is detected. If the rising edge is valid, it indicates that the infrared baseband signal is detected. Then, it judges whether the complete 12-bit data coding is received or not. After receiving, it returns to the initial state after delay synchronization (synchronization time is more than 80a) for the next 12-bit coding data detection, otherwise it enters the pulse sampling state. When the number of high-level sampled pulses is less than 10,000, it is regarded as invalid and returns to the initial state; when the number of pulses is more than 10,000 and less than 30,000, it is regarded as receiving data coding 1; when the number of pulses is more than 30,000 and less than 80,000, it is regarded as receiving data coding 0; when the number of pulses is more than 80,000, it is regarded as invalid and returns to the initial state. The serial code output by the decoding controller enters the post-cascade serial/parallel converter bit by bit. The sampling frequency of the decoding core FPGA controller is 50 MHz.
The design part of the FPGA mainly includes three modules: Digital Clock Manager (DCM), decoding control circuit and display mode control circuit. The decoding circuit includes three modules: decoding controller, signal synchronization delayer and serial/parallel converter. The display mode control circuit consists of decoder and color lamp circular display circuit. The block diagram of the logic design system of the FPGA is shown in Fig. 5. The DCM module converts the input clock frequency to the global clock signal CLK at 50 MHz, which provides the working clock for all subsequent modules. The decoding controller sampled the input baseband signal. As shown in Fig. 5, the sampled serial data was output in parallel after a serial/parallel converter [8?9]. Then the decoder converted the sampled serial data into a mode control signal corresponding to the key command to control the multi-mode display of the color lamp. To ensure signal synchronization [10], the clock cycle of shift register is [4a,] which is obtained by 50 MHz global clock frequency division. The actual test system works well and performs well. The decoding module of FPGA realizes the real-time decoding and display of infrared coding. The distance between receiving and receiving is about 20 m. In the Modesim simulation environment, the timing simulation of the decoding and mode control circuit system of the FPGA is validated, as shown in Figure 6.
A description of the simulation results is given below. For the convenience of description, the signals in Figure 6 (a) are used from top to bottom [a1,] [a2,] [a3,… ] The signal in Fig. 6 (b) is represented by [b1,] [b2,] [b3,… from top to bottom. Express. [a1] is a 50 MHz clock signal, [a3] is a 12-bit serial coded input signal 111100100000, [a10] is a 12-bit parallel code data, thermostatic element [b1] is a 2-bit mode control signal, [b2] is a color lamp circular display data code.
As can be seen from the simulation diagram, when each [a3] signal arrives, the decoder controller correctly outputs it in parallel and converts it into mode control signal 11. Under [b1] control mode, the color lights are lit in turn (low level stands for light), and the corresponding codes are 01110111, 10111011, 11011111101, 11101110, respectively. This paper designs and implements a control circuit of infrared remote control color lamp based on FPGA, which can be decoded flexibly according to the coding format of infrared transmitter and the programmable characteristics of FPGA. This design realizes the circular control of the four-channel infrared remote control color lamp display mode well. Users can freely change the circular mode of the color lamp according to the actual needs. Compared with professional chip or single chip software design technology, the parallel processing mode of FPGA logic devices makes the circuit response time shorter, the operation cost smaller, and can work reliably and stably even in strong interference environment. At the same time, with the rapid development of the technology of FPGA, its cost is rapidly reduced and its volume is continuously reduced, which has a broad application prospect in the future industry, lighting and other fields.