The structure, principle and timing of SDRAM are introduced. On this basis, the design of SDRAM controller is realized based on FPGA, and the code structure of the design is given. The simulation of the design is completed on MODELSIM platform. The results show that the design is successful. SDRAM is a synchronous dynamic random access memory (SDRAM). It has low price, large capacity and small volume. It is the main component of computer system. In the real-time image acquisition and processing system, SDRAM is mainly used as storage device considering cost performance and other factors. The control logic of SDRAM is complex. For different storage requirements, in order to make full use of the performance of SDRAM, it is necessary to design a special controller.
There are several storage arrays in SDRAM, which makes it easier to access sequentially and randomly. Such an array is called an L_BANK. General SDRAM chips take four such L_BANK..
The steps of accessing storage unit are: first accessing L_BANK, then accessing rows, and finally accessing columns. For example, HY56V641260 has row address 12BIT, column address 8BIT, memory cell width 16BIT and L_BANK number 4.
The capacity of HY56V641260 is 4*1M*16BIT. The main control pins determine the main operation of SDRAM, which is very important for designing the controller of SDRAM. As shown in Table 1, the functions determined for SDRAM pin name and pin combination. Among them, CS- is the chip selection signal, RAS# is the pass, CAS# is the column selection, WE# writes the signal. All the above signals are low-level and effective, and their different combinations realize different functions of SDRAM. When reading and writing, WE is low for writing and high for reading. Function numbers are: 1, no operation; 2, selected rows; 3 and 4, selected columns (read/write at the same time); 5, burst transmission termination; 6, pre-charging; 7, refresh; 8, mode register loading.
The timing of SDRAM is divided into initialization timing and read-write timing. Different stages of the timing correspond to different operations of SDRAM. As shown in Figure 2, initialization is divided into four stages: input stabilization period of 200us, four L-BANK pre-charging (operation 6), eight refresh cycles (operation 7), and mode register loading (operation 8). The mode register loading determines the reading and writing mode of SDRAM. Fig. 3 is a read-write sequence diagram. Firstly, select the row (operation 2).
After time tRCD, you can read/write the operation (operation 4).
Of course, select the column and invalidate the row at the same time.
A. 200us operates on a regular basis, performing empty operations. According to the timing, the implementation of the controller is mainly divided into initialization and reading and writing parts. CKE <= 0; end // clock enablement.
All the above control signals except CKE are valid at low level, so after reset, the control signals are taken at high level, waiting for initialization instructions. After receiving the initialization instructions, the rows and columns are not selected, and the write enabler can take a high level, at which time the initialization begins. The system clock takes 125MHZ, and the four stages of initialization sequence are controlled by counter counting. The first stage is 250us stable period, corresponding counting value is 25000, the second stage is pre-charging stage, which requires 20 clock cycles, thermostatic element the third stage is 8 refresh cycle pairs, each refresh cycle is 20 clock cycles, and the last stage is register mode loading. The value of INIT_REQ is 1 for the stable period of 200us, and the value of PRECHARGE is 1 for the pre-charging, and so on. After the mode register is loaded successfully, SDRAM can be read and written. After receiving the read command, the first step is to pass, so that the pass pulse value is 0 and the column pass pulse value is 1. It takes a certain time delay between line and column strobe. This time is called line strobe period, which is usually expressed by t_RCD. In SDRAM of different manufacturers, the value of gating cycle is different, usually 2 to 3 clock cycles. When the value of do_rw is jumped from 0 to 1, it shows that the delay is completed and the read-write action can be carried out. The read-write action is performed when the line-pass pulse is high and the line-pass pulse is low. Specific read or write actions are marked by the read and write tag register rw_flag.
At this point, if the data is read, after a data latency CL, the data will appear on the data bus. The model of SDRAM is HY57V641620 of hynix. Its structure is divided into four BANKs. Each BANK takes the row address of 12BIT and the column address of 8BIT. Its capacity is 1M*16BIT. At the time of simulation, BANK coded 11, CKE with high level and CSN with low level are selected. At the same time, we need to design a simulation data file to provide written data for SDRAM. The initialization simulation sequence is shown in Figure 4. For simplicity, the screenshot removes CKE and CNN signals. Figure 5 shows the reading and writing sequence. After the mode register is loaded, it enters the reading and writing sequence of SDRAM. From the sequence diagram, we can see that the row selection signal is low, then the column selection signal is low, and the WE_N signal is valid. At this time, write the data. The controller is designed to control SDRAM to store real-time images captured by CMOS camera.
In practical applications, we also need to design a read-write buffer to temporarily store the data stream of the camera. The data of SDARM comes from the read-write buffer, which replaces the data files used in simulation.