The principle of OV7725, configuration register and SCCB timing are introduced. On this basis, the design of OV7725 controller is realized based on FPGA, and the code structure of the design is given. Code design and download were completed on QUARTUS II 13.0 platform. The results show that the design is successful. OV7725 is a CMOS camera of Howe. It has the characteristics of low cost and high sensitivity.
It has been widely used in video image acquisition system. At present, although the sensitization effect of various CMOS cameras is different, the development process is similar. By configuring the camera register, the camera can collect video images according to the configuration parameters. OV7725 has 172 registers for working mode configuration.
Because of the large number of registers, configuration parameters need to be transmitted through SCCB bus. Therefore, it is necessary to design the controller to realize the parameter configuration of OV7725. Through SCCB protocol, OV7725 is configured.
Then, driven by the clock, the sensor sampled the image. After 12 bits A/D conversion, the sampled signal was processed by the DSP, and the 10 bits video data meeting the configuration requirements were output. OV7725 has 172 configuration registers. Before the sensor works properly, these registers must be configured. Otherwise, the expected image quality can not be obtained. Of course, most of these registers can adopt default values without having to reconfigure parameters. Some register addresses and descriptions are shown in Table 1.
The parameters of these registers determine the format and quality of the video stream. The order of registers configuration is arbitrary, and the order of registers configuration has no effect on the result.
SCCB protocol, called serial camera control bus, is a simplified version of I2C protocol. SCCB interface provides two buses: a serial data bus SDA and a clock bus SCL. SCCB does not support multi-byte reading and writing. In SCCB read cycle, the host must send bus stop condition after sending register address. Therefore, when Verilog implements SCCB timing, SCL pins are always set as output mode. SCCB writing cycle uses I2C writing cycle timing directly, and reading cycle needs a bus stop condition.
The SCCB reading and writing sequence shown in Figure 1. A. Bus is idle, SCL and SDA are high level. B. In idle state, the level of SDA is lowered and SCCB bus is started. Data signals are transmitted on D.SDA. When SCL is at high level, the upper level of SDA remains stable, and when SCL is at low level, the state of SDA is allowed to change. Data is transmitted bit by bit and synchronized with the clock. Data is a byte, MSB is in front, LSB is in the back. After LSB, the host releases SDA, and the slave sends the response signal. During the high-level period of E.
SCL, the SDA rises and the primary data transmission stops. The design module configures the registers. The 16BIT register type vector config_data is defined, and the configuration values of each register are obtained according to the address, which are transmitted to the SCCB protocol bus controller to implement the configuration of OV7725. Configuration data is designed as a lookup table implemented with CASE statements. SCCB read and write function is realized by state machine. According to the writing time sequence, the states of SCCB are designed as follows: W_IDLE, W_START, W_ID_ADDER, W_ACK1, W_REG_ADD, W_ACK2, thermostatic element W_REG_DATA, W_ACK3, W_STOP. The state machine is implemented by three ALWAYS processes, in which the state selection process cycle achieves the selection and transformation of the above states. The following code structure realizes state output, that is, read device ID address and data from configuration module and write them to configuration register. Wdata is an 8-bit vector that stores data to be transmitted. In idle state, the data line is high level. In the W_START state, the data line is pulled down and data is transmitted. The device address is loaded with vector wdata. In the W_ID_ADDRER state, the device address is serially output by sdat_out. In the slave response phase, the wdata vector loads the register address for transmission. By analogy, transfer register address, register configuration data, etc. The top module OV7725_TOP is designed to instantiate the above module.
The RTL diagram shown in Figure 2 is obtained. Pin cmos_clk and cmos_sdt are used as clock and data line of SCCB bus respectively to realize the reading and writing function of OV7725. On the basis of mastering the address and function of OV7725 configuration register, according to SCCB timing, the controller is designed to configure OV7725 register, so that OV7725 can output video stream format and picture quality as required. Based on QUARTUS 13.0 platform, the controller design is realized.