In recent years, network technology has developed rapidly, and has made great contributions to promote the development of various fields of production and life in society. The emergence of industrial Ethernet technology also makes it further integrated into the control layer and equipment layer of the control system network. In order to further promote the development of Ethernet technology, this paper takes the embedded network interface controller based on FPGA as the main research object. Through the brief description of the working principle of the embedded network interface controller, the hardware and software platform of the embedded network interface controller based on FPGA is comprehensively designed and analyzed.
By analyzing the traditional control system, we can see that most of them are based on Ethernet in the information layer, while different fieldbus is selected in the equipment layer and the control layer to support LAN networking. With the emergence and development of industrial Ethernet technology, Ethernet has gradually penetrated into the control layer and equipment layer from the traditional information layer. In this context, the embedded network interface controller, which takes microcontroller and microprocessor as the hardware core, is integrated into the industrial equipment such as CNC machine tools and manipulators, and promotes its effective connection with Ethernet to improve the control efficiency of the equipment, which has become the key work to be emphatically carried out in the field of industrial ethernet. The analysis of embedded network interface controller shows that DM9000E chip is chosen as the main controller to realize the data exchange between interface data information and upper ethernet. Based on 32-bit microprocessor S3C2410 and embedded Linux system, the protocol and data processing are realized. Then, the processed data is transmitted to the lower device terminal, and at the same time, it will come from the lower device terminal. The data is processed and the protocol is implemented, which is transmitted to the Internet via DM900E chip. The core controller FPGA in the design is EP2C8Q208C8 model FPGA of Altrea Company, which is the key component of Altera Cyclone II series devices. Its application mainly concentrates on terminal market, such as computer, industry and automobile. The number of PLL, global clock network and logic unit in FPGA is 2, 8 and 8256 respectively. In addition, it has 36 M4K RAM and 138 I/O ports. It has many advantages such as low cost, high performance, low power consumption and strong expansion. However, because its internal block random access memory, that is, the capacity of BlockRam can not meet the storage requirements of VxWorks and Linux, the Flash of 32MB is introduced as the main storage module of the image and bootloader. At the same time, the 256MB’s new generation memory DDR2 provides the program running space, and 1 RS232 communication interfaces and GPIO are introduced to debug [2]. Firstly, Temac, a tri-state Ethernet media access controller, is designed. The original language of Temac includes a pair of 10/100/1000MB Ethernet Macs.
By analyzing the Virtex devices, we can see that the number of Ethernet MAC modules in Temac is mostly 4, so it fully conforms to the IEEE802.3 specification. The module structure of Ethernet Mac is designed. According to the type of external interface, the interface module can be divided into physical interface, client interface and control interface.
Each Mac also has an optional management data I/O interface. With this interface, access to management register in physical layer and physical interface management register of Ethernet Mac itself can be realized. Secondly, in order to improve the comprehensiveness and reliability of the design, the physical interface of Ethernet Mac is divided into GM II (cryptographic device application interface) and SGM II (serial Gigabit coal independent interface). When GM II interface is selected, the external 88E1111-RCJ configuration register is the physical layer chip, while SGM II interface is selected, the number of Temac connection with the external physical layer can be reduced. Using pulse code modulation / physical media adaptation layer module, that is, PCS/PMA works together with RocketIO transceiver, so as to provide Temac with all the functions of GBIC or small SFP optical transceiver, thereby effectively preventing the problem of structure and data redundancy caused by external physical layer chips in the application process of 1000Base-X network [4]. It should also be noted that in order to simplify the design and lay the foundation for the subsequent on-chip system integration, PLB control bus should be introduced. The PLB_Temac bus core has an adjustable size of FIFO queue and direct memory access engine, which further simplifies the construction of embedded PowerPC system.
In the customization of on-chip system, its core work is the design of system main frequency and the selection of quality, data cache size and external data instructions. Its peripheral IP includes control interface IP under DDR2 protocol standard, external Flash and GPIO interface IP and PLB_Temac network interface IP. In Flash module, we need to design its type and read-write time, and introduce the debugging serial port Uart 16550 for debugging. At the same time, the DCM real-time clock management module and the RAM area of the FPGA need to be set up to realize clock management and.
boot file storage functions respectively.
In terms of peripherals, the unified allocation of communication addresses between PLB bus and PPC is implemented, and the memory space address of DDR2 is allocated to the initial state of 0*0. The controller under DDR2 protocol standard is designed, which adopts Memory Controller module produced by XPS, and designs DDR2 chip manufacturer, chip memory size and data digit. It also needs to be explained that besides the above modules and function configurations, two separate PLB buses need to be set up and connected with PPC line, so that both of them can be used as instructions of PPC. Bus and data bus.
In addition, the PLB_Temac module of XPS is added to the MAC unit to realize the interface control [5]. The design of peripheral circuit needs to take field programmable gate array FPGA as the core and extend all kinds of devices step by step. When setting the pins of fpga, the voltage of different voltage-controlled crystal oscillators should be fully considered. Considering that DDR2 and PHY chips can operate under the voltage of 2.5V and 1.8V respectively, and the required voltage of peripheral is 3.3V, they are connected with DDR2 and PHY chips.
The foot power supply shall provide 2.5V and 1.8V voltage respectively, while the power supply of the pin connected with the peripheral device shall provide 3.3V voltage.
In addition, the DCM clock management module should be placed at the global clock pin to realize the management and transmission of clock signals. In DDR2 routing process, it is necessary to ensure that the data line and address line are equal in length, and the data line and address line should be controlled within 10 Mil (one thousandth of an inch) and 20 Mil, respectively. In addition to differential equal length setting, the clock line should also be guaranteed to be longer than the address line, so as to avoid clock signal acceptance delay. Firstly, the transplantation of BSP is analyzed. Based on the platform of microprocessor and embedded operating system, the BSP generator BSP_GEN in EDK (embedded development kit) can automatically generate BSP for user tailoring, which not only supports the initialization of Boot code and device driver, but also supports initialization of the operating system itself. Using BSP_GEN, the related drivers of the programmable logic integrity solution are packaged and coexist to the BSP subdirectory. At the same time, the integration of the above drivers with the integrated development environment of the Vxworks operating system is integrated seamlessly, so as to shorten the development cycle of the controller. However, it needs to be explained that the BSP generator BSP_GEN is essentially a fixed BSP template, so it is difficult to correctly and comprehensively reflect the RAM/ROM memory mapping, and it can not support users to drive by BSP_GEN. Based on this, we need to make corresponding improvements to BSP generated by BSP_GEN: 1) modify the RAM and ROM geology and serial port baud rate in Makefile files. The port is properly set up; 2) introducing the corresponding driving files that are difficult to integrate with the Vxworks operating system, and configuring the Ethernet parameters in systemNet.c to achieve the accurate setting of MAC addresses; 3) in accordance with the relevant configuration in EDK, thermostatic element Cache prohibits and modifies systemLih.c to ensure that the information displayed by the generator is accurate and correct, and the IP address of the host is scientifically set up. Secondly, UDP, the user datagram protocol of the Socket end of the two-way communication connection, is programmed. After the configuration and modification of BSP is completed, it enters the process of UDP server program writing. In the aspect of network communication, most of them can be realized by Socket.
The programming chooses the data communication mode based on client/server.
The analysis of Vxworks system shows that it provides standard BSDsocket for users to support the transmission of UDP protocol, and allows the connection with remote computers, so as to realize the data transmission based on UDP protocol. The specific process of the server work is as follows: 1) the server calls Socket (), establishes socket socket, and calls bind () to bind socket with local network address for accurate identification by client; 2) the server calls listen () to put socket in the ready receiving state and indicate the length of socket request queue, and then calls accept () to accept client connection; After completion, the server process will enter a relatively blocked state, making the relationship between the client and the server asymmetric, while the server takes the lead in starting, and according to a certain moment, the client requests a passive response. The specific workflow of the client is as follows: 1) calling Socket () function to establish the socket interface between the client and the system, and at the same time, returning the ID number corresponding to each socket; 2) initializing the structure of a set of interfaces and giving it the return ID number and the IP address and IP port number of the server, and then calling the connection () function as the main parameter of the correlation function connect (). Promote the client to actively connect with the server to achieve data transmission. Finally, the system is debugged.
In order to ensure the validity of system debugging, we use ChipScope Pro embedded logic analyzer to capture and analyze the internal data of FPGA on-chip system, in order to achieve the purpose of rapid debugging and verification optimization. In addition, according to the simulation results of real-time data captured by the memory of embedded logic analyzer in the process of reading and writing, the timing of the interface controller is optimized, and the debugging and verification of the controller are completed. In this paper, the working principle of the embedded network interface controller is briefly explained. Based on a brief introduction to FPGA, the hardware part of the embedded network interface controller is designed from the aspects of Temac, on chip system integration and peripheral circuits. The software of the embedded network interface controller is also discussed from the board level support package and its modification, and the UDP program under Socket. Part unfolds the design. The research results show that when FPGA is added to the operating system, it is easier to receive and send network data. It has important practical significance for promoting the development of industrial Ethernet technology and realizing the effective connection between industrial device interfaces and Ethernet.