In order to solve the problem of data storage in radar digital beamforming system, a FLASH controller based on FPGA is designed in this paper. The read-write control of FLASH is realized by finite state machine, and the design is verified by simulation in modelsim. The correctness and reliability of the design are proved by hardware test. This method makes full use of the advantages of flexible design of FPGA and fast reading and writing speed of FLASH storage. It has the characteristics of low cost, strong compatibility and easy engineering implementation. With the rapid development of digital array radar, thermostatic element the requirement of digital beamforming is getting higher and higher, and a large amount of data needs to be stored in real-time processing.
Because the storage capacity of the FPGA itself is very small, it can not meet the storage requirements in the process of digital beamforming.
In order to solve this problem, the hardware architecture of FPGA FLASH is adopted, and the storage control of FLASH is realized by FPGA, which greatly expands the storage capacity of the system. Taking EP4SGX230 of Altera and AM29LV065D of AMD as examples, the design of FLASH controller based on FPGA is described in detail. The interface operation between FPGA and FLASH storage is realized by writing synchronous finite state machine in Verilog HDL language. FLASH chips choose AMD29LV065D model of AMD company. The main characteristics of this type of chip are: 3.3V single power supply, internal programming and erasing operation; 64Mbit storage capacity, which is divided into 128 sectors, each sector can be read and written independently without affecting the data of other sectors; ultra-low energy consumption, typical reading operation only needs to be eliminated. It consumes 9 mA, 26 mA for typical erase/programming operation and 200 nA for typical static mode. It is simple to operate, and it only needs to write instruction sequence to FLASH internal command register in specified time sequence. A [22:0] of AMD29LV065D chip is the address bus, DQ [7:0] is the three-state data bus, and other signals are the read-write control and operation signal of the chip. Except for power supply, clock and reset and several configuration clock pins, the other pins of the FPGA can be used as universal I/O. Therefore, when connecting with FLASH, it is only necessary to connect the common I/O pin of the FPGA to the FLASH pin. The FLASH circuit diagram is shown in Figure 1. AM29LV065D chip of AMD company has three speed levels of 90ns, 100ns and 120ns, which can fully meet the timing requirements of the work of the FPGA. According to the data handbook of the chip, the finite synchronous state machine is designed in Verilog HDL language to realize the sequence state transition of FLASH control instruction sequence, so as to complete the erasure, reading and writing of FLASH. Erase operation is divided into sector erase and chip erase. The whole erase process is: the first clock cycle writes AAH data at address XXXH, the second clock cycle writes 55H data at address XXXH, the third clock cycle writes 80H data at address XXXH, the fourth clock cycle writes AAH at address XXXH, and the fifth clock cycle writes AAH at address XXXH. Write 55H at address XXXH and 10H at address XXXH in the sixth clock cycle. The process of sector erasing is the same as that of whole erasing, except that the sixth clock cycle writes the corresponding sector address at the address and 30H at the data. Then wait for the chip to finish the erasing work. After the FLASH sector erase or the whole chip erase is completed, all data bits in the corresponding sector or the whole chip are set to `1′. Writing operation of FLASH chip includes erasing operation and programming operation. Before writing to the corresponding sector, the data of the sector must be erased.
After the erase operation, the data of the whole sector is set to FFH, that is, all data bits are in the state of’1′. When writing data, only the data bits of corresponding units can be changed from `1’to `0′. The erasure operation is described in Section 2.1. The programming process is as follows: the first clock cycle writes AAH data at address XXXH, the second clock cycle writes 55H data at address XXXH, the third clock cycle writes A0H data at address XXXH, and the fourth clock cycle writes corresponding data at address XXXH. It can complete the write operation of single data, and the write operation of the whole sector can be realized by multiple cycles. FLASH read operation is relatively simple, the process is: input address XXXH, read the output data XXH. Finite state machine (FSM) is used to realize the jump of erasing, reading and writing states of FLASH. There are 17 states in this paper.
Among them, state 0 is IDLE state, state 1 is working mode judgment state, state 2-7 completes block erase operation, state 8-12 is write state, state 13 is write end judgment state, state 14 is write end state, state 15 is read end state, state 16 is read end state.
When the system works, the first step is to judge the working mode. When the mode of work is to write, erase the sector of the write operation object first, then write the data in turn, and judge the end of the block after each data is written. If the current block has been written, the state jumps to the erase state of the next sector to be written until all the blocks are written, and the state jumps to the IDLE state. When the mode of work is read, read addresses directly in turn, and judge the end of each data read until all addresses to be read are finished, and the state jumps to IDLE state. FLASH chip returns to read mode after reset and command operation errors. As long as the output enabling signal OE # and the chip selection signal CE # are at low level, the data of the corresponding address storage unit on the address bus can be sent out. When the command is sent to flash memory according to the specified command sequence, the state machine automatically completes the corresponding operation. The state bit of FLASH is RY/BY# pin. In the process of FLASH operation, if the pin output low level indicates that FLASH is busy, it becomes high level after operation, indicating that FLASH returns to idle state. In this paper, a FLASH controller based on FPGA is designed.
The read-write control method of FLASH memory using synchronous finite state machine is described in detail. The correctness of this method is verified by simulation of Modelsim timing.
This method has been successfully applied to the design of digital beamforming system, and the practice has proved the correctness and reliability of this method. The design method introduced in this paper is generally applicable to read and write control of NOR FLASH memory in FPGA.