Intelligent traffic control system program is designed with VHDL language and downloaded to the FPGA/CPLD chip in QUARTUS II system, which achieves the desired design effect.
The design of traffic information control system based on FPGA/CPLD chip can reduce the cost of design and shorten the design cycle due to the traditional chip design, which has a greater advantage than the traditional design method.
According to the control requirements of traffic signal system, a set of red lights, yellow lights, green lights and digital countdown timers are designed and arranged in east-west direction and north-south direction of each road. The design of the system completely sets the turn-on and turn-off time of the east-west and North-South tricolor lamps according to the requirements. The top-down design method is adopted in the design.
The functional circuit of the system is divided into five modules: basic traffic lights, dot matrix, music, detection and priority traffic, and then developed for each module. Traffic light controller is designed, compiled and simulated under Quartus II environment.
It is designed by hierarchical mixed input mode, thermostatic element that is, using top-level schematic design and VHDL language design. The core module of the system controls the alternate lighting of red, green and yellow lights from east to west and countdown of digital tubes. Functions are as follows: “East-West direction green light through the digital tube SM2, SM1 countdown 50 seconds, turn to yellow light flashing 10 seconds, and then to red light 60 seconds.
Red, yellow and green lights in the north and South direction, countdown 60 seconds, flicker 10 seconds and countdown 50 seconds by digital tube SM6 and SM5, respectively, continuously circulating.
When there are priority vehicles, such as 120 ambulances in daily life, 119 fire alarm vehicles, etc. It immediately turns traffic lights in normal operation into red lights in east, west, north and South directions, and digital tubes flicker and time is suspended.
Traffic lights return to normal when priority vehicles are detected to leave.
The lattice module is made of 16 rows and 16 rows of light emitting diodes. When the green light is on, it shows an intersection and an arrow indicating the direction of people’s passage inside the intersection. It is used in conjunction with the “Priority Pass” module.
When there are priority vehicles coming, the arrows inside the intersection in the lattice disappear, indicating that the vehicles in the east, west, north and south directions can not pass. This module stores several beautiful songs in advance. When pedestrians wait for the red light, they ease people’s anxiety. When the red light in different directions is on, it can play different songs. The function of this module constantly detects the normal operation of red, green and yellow lights in the East and West directions. If there is abnormal detection, the horn will send out alarm signals. After completing the system design simulation, pin binding was carried out and downloaded to EP1K30QC208-2 of ACEX1K.
Quartus II6.0 waveform simulation is used to simulate each module. On the basis of ensuring the correct function of each module, five modules are connected to form a complete design. Quartus II6.0 is used to simulate the whole system. Through the system simulation, test and function test, the design of the whole system meets the design requirements. Finally, the program is downloaded to Altera’s FPGA chip (EP1K30QC208) by using Quartus II6.0 software. After verification, the result of the design achieves the expected effect.