Aiming at the shortcomings of the existing design scheme of brushless DC motor controller, a design scheme of brushless DC motor controller based on FPGA platform is proposed. The speed and current double closed-loop control system of motor is designed by using FPGA. The hardware of the system includes the control circuit with the core of FPGA and the drive circuit with the motor as the object. The software of the system adopts Veri. LogHDL generation speed and current sampling module, motor drive commutation module, PWM generation module, etc., while displaying the operation status of the control system on VGA. The test results of the controller show that the designed controller can make the motor reach the given speed within 1 s after starting and keep the steady value within ( 2%) after 1 s. It shows that the control system has high control accuracy and good stability. Brushless DC motor has the advantages of high efficiency, good speed regulation performance and simple structure, and is widely used in the field of electric drive. However, the use of electronic commutation instruments instead of traditional mechanical brushes brings many difficulties to the design of the controller. The current fluctuation in the commutation process easily interferes with the control chip, which leads to the instability of the system. With the increase of the complexity of the control strategy, the longer the closed-loop control period of the system will also lead to the decrease of the real-time performance of the control system [1?4]. In order to effectively solve the above problems, improve the control accuracy and robustness of BLDCM control system, and provide a good test platform for the study of motor control algorithm to avoid the possibility of program running, this paper designs a BLDCM controller based on the FPGA platform. The control system takes the FPGA as the core and adopts the hardware description language. The brushless motor is controlled by means of electrical isolation in the hardware circuit to improve the stability and anti-interference ability of the control system.
The hardware circuit of the brushless DC motor controller is shown in Figure 1, which is mainly composed of control circuit and motor drive circuit. The control circuit processes the given speed signal and the output signal of each sensor, and then realizes the speed control of BLDCM by the corresponding control method, such as the forward and reverse of the motor, the increase and decrease of the speed and the start/stop of the motor. The motor driving circuit amplifies and isolates the output signal of the control circuit to realize the control of strong current by weak current. Man-machine interaction can realize motor start, stop, reverse and setting parameters such as given speed and PI, so as to facilitate users to control and understand the operation status of the control system. The software design adopts modular programming idea, and divides the total task of the controller system into several functional modules such as speed sampling, current sampling, motor-driven commutation control, PWM modulation, human-computer interaction and digital PI regulator. Each module is implemented by hardware description language Verilog HDL. The main program flow of the system is shown in Figure 2. The system initialization mainly includes clock initialization, LCD and VGA initialization settings, A/D initialization, PI and speed parameter settings, etc. [6?7]. All ports in the parameter setting module receive the level signals from the button anti-shake module, modify the PI parameters of current and speed according to the rising edge of the level signals and the corresponding combination, thermostatic element and change the direction of addition and subtraction and pause signals of the ordinary button input into the input of the self-locking switch. At the moment of motor start-up, 40 ns is used as sampling interval to detect Hall signal input by Hall port. If the Hall signal obtained by two sampling is different, the internal counter is added 1. The time of triggering alarm is set by setting the overflow value of the counter. The time set by this design is 3 s. When the bus current of the motor is converted to the maximum value of the set current after A/D real-time conversion, if the bus current of the motor is larger than the set limit value at the current moment, the alarm will be given within 2 ms of the delay time, so as to achieve the purpose of over-current protection [8]. The input signal of the speed detection and PI operation module is the pulse signal of the photoelectric encoder. The photoelectric encoder rotates one circle to generate 1 024 pulses. If the accuracy is to reach one circle per minute, the sampling time is set to [601 024=] 0.058 593 75s. The pulse of the photoelectric encoder received in this time is the corresponding speed per minute [9].
The sampling time is controlled by a timer, and the reading of the PI operation values of [ki] (speed loop integral parameter), [kp] (speed loop proportional parameter), [cp] (current loop proportional parameter), [ci] (current loop integral parameter) and ad_in (current sampling A/D conversion value), Rond (real-time speed) and speedin (setting speed) are designed in time sequence. Set before PI operation. After the operation, the increase/decrease value of PWM duty cycle register is adjusted from the action port output. The output upper limit of the speed loop is the maximum input value of the current loop, which can ensure that when the current exceeds the output upper limit of the speed loop, it can be automatically adjusted and maintained in a certain range. The duty cycle addition and subtraction module, as shown in Figure 3, inputs 14-digit values with symbolic bits from the erond port, adds or subtracts duty cycle registers and the next 13 bits through its first symbol bit judgment, and sets the maximum and minimum differences to limit the maximum and minimum duty cycles (96.3% and 23%). In order to facilitate the start-up of the motor, the duty cycle register has an initial value of 1 000, or 33% duty cycle. As shown in Figure 4, the PWM generation module inputs the value from the cont port from the duty cycle module. Compared with the counter which increases with the system clock, if the counter value is larger than the input value of the cont port, it outputs the low level; if it is smaller than the input value of the cont port, it outputs the high level. The structure block diagram is shown in Fig.
5. The VGA LCD module is shown in Figure 6. When the system is powered on, the coordinate axis is displayed on the VGA LCD.
The horizontal axis represents the time in S and the minimum scale is 0-7 s in 0.1 s. The vertical axis represents the speed in r/min and the minimum scale is 100 r/min. The display range is 0-5 000 r/min. The red line shows the set value of the input speed by the setrond port and the blue line. Display the position of 2% and 5% of the set speed. When the stop port is input at a high level, the LCD will display the scatter plot of the motor speed varying with time, and the time interval is 0.1 s. At the same time, the Chuan 1 and chuan2 ports will output corresponding pulses to control the serial module to output the current motor speed value every 0.1 s. If the pause port input high level, the scatter plot displayed on VGA LCD will keep the current display interface and no longer refresh, and the serial port will no longer output motor speed [10]. In the experiment, 48V/500W brushless DC motor is used for debugging. The rated load current of the motor is 15A, the rated no-load current is 1A, the rated speed is 4 500, and the speed range is 0-5 900 r/min. The start/stop, forward/reverse and acceleration and deceleration of the motor are controlled by human-computer interaction in real time.
The test shows that the control system has good robustness when the speed regulator parameters [P=1.56, I=0.43,] the current regulator parameters [P=1.37,] [I=] 0.87. Figure 7 shows the state of the controller in different speed control stages when the motor is idle. From Fig.
7 (a), it can be seen that the control system can reach steady state within 0.9 seconds from start-up to speed rise to 2 000 r/min, and then keep within the range of <2% of steady state value. The overshoot of the system is 7.3%, and the steady state error is about 35. From Fig. 7 (b), it can be seen that the control system can reach steady state within 0.8 seconds when the motor rises from 2000 r/min to 5 000 r/min, and there is no overshoot in the system. The steady state error is about 30. From Fig. 7 (c), it can be concluded that the speed of the motor decreases rapidly from 5 000 r/min to 2 000 r/min in 1 s, and maintains in the 2% range of steady state value after 1.5 seconds. It can be seen that the system runs stably, achieves steady state quickly, and can accurately control the speed of the motor. This paper uses FPGA to realize double closed-loop PI speed regulation control of BLDCM, uses Verilog HDL to realize PWM, speed sampling, motor commutation and other modules, and uses VGA to display the operation status of the system. The design and manufacture of software and hardware of BLDCM controller are realized. The experimental results show that the controller has high performance. Control accuracy and better stability.