In the avionics system, the application and demand of discrete digital circuits are increasing, while the traditional discrete interface chips have low integration and high power consumption, and it is difficult to guarantee the stability and reliability of discrete quantities in harsh environments. Based on the above limitations, this paper introduces a new discrete digital interface conversion chip, which can convert 28 V aviation power supply level to TTL level. Because of its high integration, low power consumption and stable performance in harsh environment, it has a wide application prospect. At the same time, a control method different from the traditional “CPU dedicated chip” is proposed for the read/write operation of the chip. Programmable logic devices (FPGA) are used to control the chip, control logic is written in VHDL language, design is synthesized in Xilinx integrated development environment, and test codes are written to simulate. The results show that this method can not only control the read/write of the chip, but also greatly improve the system’s ability to process data, and has higher stability and reliability. In recent years, China’s aviation industry has developed rapidly, and all kinds of airborne equipment are being upgraded. Especially in the avionics system, as the control core of the electronic equipment on the aircraft, the airborne computer needs to collect more and more discrete signals to obtain the working status of the current system. At the same time, it needs to output a large number of discrete signals to send instructions. Therefore, discrete interface circuits have been more and more used in avionics systems, and gradually become the basic component of avionics circuit system. However, with the increase of discrete quantity, the traditional discrete quantity interface is not only low in integration, but also difficult to ensure the reliability of data in harsh environment.
In this paper, a new type of HKA03201 discrete digital interface chip is proposed, which has the functions of self-checking, error isolation and double redundancy, so the reliability and stability of data are improved. At the same time, due to the miniaturization of integration, it has certain advantages in power consumption, cost, area and weight. There are many methods to control the read/write of the discrete interface chip. The traditional method is that the CPU directly controls the chip through the program, which will occupy a large number of CPUs in the program, greatly weaken the processing capacity of the CPU, thus reducing the reliability of the system. In this paper, programmable logic FPGA device is used as the controller of discrete interface chip. The control logic is written in VHDL language. Through a bridge logic, the control of HKA03201 chip can be realized. This can greatly reduce the working time of CPU, thus improving the system’s ability to process data and enhancing the stability and reliability of the system. Sex. Usually, tens to hundreds of discrete signals are needed in the system. These discrete signals are 28V aviation power supply level. They can not be connected to the avionics system as control signals. Therefore, it is necessary to convert 28V aviation power supply level to TTL level through circuit conversion. If hundreds of circuits are converted by using external circuits and devices, It occupies a large amount of space, and consumes a large amount of space in the area, weight, power consumption, volume and other aspects of the control board, and the cost is high [1]. Therefore, this paper proposes a new discrete digital interface chip, which is an interface integrated circuit used to convert discrete data into TTL level. The circuit integrates 32 discrete input channels, and each input channel supports three discrete input forms: 28V/Open, 28V/GND and OPEN/GND. Because of the miniaturization of the integration, the area, power consumption and cost of the control board have been greatly improved. The reference level outside the chip is configured to adapt to the discrete signals of different aviation levels, which makes the chip application more flexible and more adaptable to the system. The maximum voltage withstand of the port can reach 55 V, which can prevent the impact of the discrete input port surge voltage and increase the reliability of the chip. The chip can convert 32 discrete quantities to TTL level, and provide SPI and asynchronous memory access interface. Discrete port can be configured in DMA mode and self-scanning mode. When 16 bits are input, it can be configured in double redundancy mode. The input port provides active fast release function, thermostatic element built-in oscillator and double clock redundancy. The internal structure of the chip is shown in Figure 1. Built-in oscillator with dual clock redundancy. Delayed sampling input is used to shield the high frequency jitter and the shielding time can be configured to meet the requirements of shielding different discrete jitter time. Due to the influence of parasitic capacitance and inductance on the chip peripheral, the high frequency jitter will occur at the instant of acquisition of discrete quantity acquisition unit. In practical operation, the high frequency jitter must be shielded and the delay is adopted. When sampling the input signal, it corresponds to the bsel pin in the chip. The chip defaults to self-scanning mode, and configures the DMA mode by configuring the internal register dma_ch_reg. When the Redundant port of HKA03201 is set high, the chip enters the redundant mode. Check pairs of ch_in and ch_in were formed. ch_in corresponded to ch_in and ch_in corresponded to ch_in and so on. When the chip has internal function error, the falut signal is set low. Data The corresponding chip, Pin51?66, is an asynchronous read-write bidirectional port for asynchronous configuration and reading of registers. For the control of HKA03201 chip, the traditional method uses “CPU dedicated chip”, takes CPU as the control core, and reads software in memory through CPU to realize the control.
Although the method of software implementation is simple and easy, it will take a lot of CPU time for a long time, weaken the ability of CPU to process data, and reduce the reliability of the system [2?3]. In view of the above situation, combining with the current mature technology of FPGA, by burning program logic into the programmable logic device (FPGA), these logic controls the HKA03201 chip in a certain time sequence. The logic is designed by VHDL language from top to bottom, and the logic designed by VHDL language needs to satisfy the reading and writing sequence of HKA03201 chip. In this way, the output end of the FPGA is connected with the input end of the HKA03201 chip, and the signal matching the reading and writing sequence of the HKA03201 chip is output by the FPGA to control the HKA03201 chip, thus realizing the discrete signal. Conversion between TTL level and TTL level. By replacing the traditional design structure with this method, the reliability and anti-interference ability of the system are greatly improved, and the cost is low. This paper uses Xilinx Virtex? 5 series of FPGA as the hardware carrier, ISEDesignSuite as the development environment, and VHDL language to write control logic to realize the control of HKA03201 chip. The structure of the control circuit is shown in Figure 2. According to the analysis of real-time signal, the chip provides two interfaces for data interaction with CPU, namely serial (SPI) interface and asynchronous interface. The interface_sel port chooses the interface mode, the high level is the serial interface (SPI) and the low level is the asynchronous interface. According to the previous chip introduction, only when the chip chooses asynchronous interface, can the port data end be checked. Therefore, asynchronous interface is chosen to communicate. CPU accesses discrete digital interface chips by bus address query. When accessing the asynchronous interface, we need to configure the read-write signal r_wn, asynchronous writing at low level and asynchronous reading at high level. Write operation is used to configure the internal registers of the discrete digital interface chip, while read operation can obtain the current status of the internal registers of the chip. Because of the bridge design, the output signals of the FPGA must conform to the reading and writing sequence of the HKA03201 chip, so the finite state machine (FSM) should be constructed to meet the timing requirements of the system when the logic of the FPGA is written. According to the sequence diagram of the read operation of HKA03201 chip, as shown in Figure 3, when the read operation starts, it first needs a high level of r_wn, i.e. a high level of output from the corresponding HKA03201_R_or_W_N pin of the FPGA. At the same time, the CPU will send the address signal to ADDR through ADDR address bus, and then send the address signal to HKA03201 chip through the output port of the FPGA HKA03201_ADDR. Because these two steps are first reflected in the reading sequence, they are named RD_WR_ADDR_SETUP as the first state. According to the sequence diagram, after 10 ns, the CS_N signal is set low, the chip selection is valid, and the read operation is started. The data is read out through the dout port, and the state life is Chip_select. The waiting time of 10 ns can be counted down by counter in VHDL logic code. After reading, the CS_N signal is set to a low level, while the ADDR and R_W_N remain valid (low level). This state is called RD_WR_ADDR_HOLD. Finally, all signals are restored to the reset state and re-enter the IDLE state.
To build a state machine in VHDL, it is necessary to define signals by enumerable state types. Then the state machine process is established and the state transition is defined in the process. Here, the sensitive signal is set up. According to the changes of clock signal and sensitive signal, the state of the state machine is changed, and finally the time sequence required for HKA03201 chip is completed. Write operations can perform the same logical design as read operations. At the beginning of the write operation (r_wn is low), input the address that needs to be written to the data register, and the R_W_N signal is set low, which is called RD_WR_ADDR_setup. Then the CS_N signal is set low, the chip selection is valid, and start the write operation. The data is written through the din port, and this state is destined to be Chip_select. After the write operation, the CS_N signal is set high while the ADDR address signal and R_W_N signal are still valid. This state is named RD_WR_ADDR_Hold. Finally, the CS_N signal is set low to end the write operation. The timing diagram of the write operation is shown in Figure 4. Because idle is the starting point and end point of state in the whole sequence diagram of read/write operation, idle, as the first item after when, lists the conditions of state transition to other states and writes the flow chart of state transition. Fig. 5 shows the whole state transition process of HKA03201 chip [4?5]. According to the above logic and state transfer, PFGA can control the read and write of the chip according to the sequence of HKA03201 chip.
In the development environment of ISEDesignSuite 13.3, the design input and synthesis simulation are carried out with VHDL language, and the design code is downloaded to the FPGA [6?7]. In order to verify the correctness of the design, a simulation tool ISE Simulator Lite (or third-party software modelsim) is used to verify the performance of HKA03201 chip.
In the simulation, the author compiles the test test program of the client, which sends the commands RESET, READ, WRITE to the FPGA controller, and provides the working clock and control register parameters. Figure 6 and Figure 7 show the simulation sequence diagrams of the chip in the process of reading/writing, respectively. By validating the simulation sequence diagram, it can be found that the timing of the simulation results is exactly the same as that of the read/write operation required in the instructions of HKA03201 chip, which proves the feasibility of reading/write operation on HKA03201 chip by FPGA. Through debugging at board level, it is found that the controller designed in this paper can not only fully meet the need of multi-channel discrete variable to TTL level conversion in avionics system, but also has simple system design, stable performance and high flexibility. It can be used in different high-performance and high-requirement systems to achieve the desired goal. The bridge method can be extended to other applications by controlling HKA03201 chip with PFGA.