This paper briefly introduces the characteristics of ARINC 429 bus and HI-3582 bus controller. Combining with engineering practice, the design idea and method of HI-3582 interface of ARINC 429 bus controller based on FPGA are given. ARINC 429 bus is the standard of civil aviation digital bus transmission developed by Aviation Radio Corporation of America. It specifies the flow of information and the format of basic data words for avionics equipments using this bus. ARINC 429 bus is a one-way transmission bus. Information can only be output from the sending port of the communication device, and then transmitted to the receiving port of other devices connected with it that need the information. When bidirectional transmission between two communication devices is required, an independent transmission bus is used in each direction.
ARINC429 communication adopts bipolar zero-return tristate code modulation mode, which has the characteristics of convenient interface and reliable data transmission. It has been widely used in navigation and positioning systems, communication systems and other airborne electronic equipment. In this paper, the characteristics of HI-3582 bus controller chip ARINC 429 developed by HOLT company are introduced, and the design idea and method of interface based on FPGA are given. HI-3582 produced by HOLT INTEGRATED CIRCUITS is an ARINC429 protocol chip with high performance and price. At present, the general scheme to realize the interface with HI-3582 is to use single-chip computer or DSP to directly control the receiving and sending of data. The disadvantage of this scheme is that the HI-3582 has more discrete control signals and needs a large number of universal I/O ports, which is more complex to implement under the situation of the shortage of general IO resources. Moreover, when the amount of data is large and the transmission and dual-receiving channels work simultaneously, the processing time of the system is longer, which affects the efficiency of the system and is easy to cause. Data loss. In this paper, the design of interface between HI-3582 and FPGA is proposed. With the rich I/O interface of FPGA, thermostatic element all the interface pins on HI-3582 chip are connected directly in the form of IO. The state control mechanism is established in the FPGA to realize the data receiving and receiving control of HI-3582 chip. This design can greatly reduce the occupation of I/O resources for single-chip computer or DSP, improve the efficiency of single-chip computer/DSP, and improve the response speed to HI-3582 interrupt request. Software design as a whole. In this design, ARINC 429 bus transmission rate is 12.5k low speed, data update is completed by DSP through address line and data line. In the design, a sending FIFO cache and a receiving FIFO cache are built in the FPGA, which are used to store the data to be sent from the DSP and the data received by two ARINC429 buses, respectively. When FIFO is sent, it does not start sending data in space-time, and generates the sending sequence of HI-3582. When receiving data, the FPGA judges and reads the data according to the receiving status flags D/R1 and D/R2 of HI-3582 in turn. When D/R1 or D/R2 is low-level, it starts data reception, generates the receiving sequence of HI-3582 to read the data in the corresponding receiving buffer of HI-3582, and then writes the read data into the receiving FIFO. When the amount of stored data in FIFO buffer reaches the trigger depth set by programming, the interrupt signal of DSP is generated to inform the DSP to read data. Design of Data Read-Write State Machine. Because of the strict logical order and timing relation of the reading and writing operation of HI-3582, it is very suitable to use state machine to describe it. So this design uses finite state machine to realize reading and writing HI-3582 data.
Figure 2 is a state transition diagram for reading and writing HI-3582 data. IDE: Initialization control register. S0: Transmit and receive control. S1: Read and send data. S2: Send control. Control the sending control sequence of PL1, PL2 and ENTX to produce HI-3582 in turn, and send out the data. S3: Receive control 1. S4: Receive control 2. S5: Cache receives data. It generates a FIFO write signal, writes 429 read data words to receive FIFO, and detects whether the amount of stored data in FIFO reaches the trigger depth of programming settings.
When the trigger depth of programming settings is satisfied, an interrupt signal is generated to notify the DSP to read data. Return to receive and receive control status after completion. Timing design of transceiver control.
When reading HI-3582, because ARINC 429 bus uses 12.5k low speed in this design, a counter is synchronized with 1MHz clock in the FPGA. The SEL is low at the first rising edge of the clock, and the HI-3582 data line is high resistance. The EN1 is low at the second rising edge of the clock, and the value of HI-3582 data line is assigned to 32 bit temporary register at 16 bits low. SEL and EN1 are high in the third clock rising edge and HI-3582 data line is high resistance; EN1 is low in the fourth clock rising edge, and the value of HI-3582 data line is assigned to 32-bit temporary register 16 bits high; EN1 is high in the fifth clock rising edge; and FIFO writing signal is low in the sixth clock rising edge, resulting in a FIFO writing pulse. Write the temporary register value to FIFO.
In this way, the effective time of reading an ARINC 429 data word is 6 clock cycles (6us), which fully meets the requirements of reading timing. Similarly, when writing HI-3582, PL1 is generated according to the above method, PL2 and ENTX start the sending operation, and continue sending the next ARINC429 data word when TXR is high.
According to the method introduced in this paper, based on the XC4VLX40-FFG668 of Xilinx Virtex?-4 series of FPGA chips, the interface design of ARINC 429 with HI-3582 has been successfully realized, and has been applied to practical equipment to meet the system requirements.