The structure, timing and related concepts of SDRAM are introduced. On this basis, based on the top-down design idea, the controller module is divided into two parts: internal command generation and command output. Based on verilog, the two modules are implemented and the top-level entity is completed. Tests show that the controller is effective. SDRAM is synchronous dynamic random access memory, which has large capacity and fast storage speed. When designing a video image system, we need to store a large amount of data. SDRAM is used as memory device. Therefore, it is necessary to design SDRAM controller. This system adopts SDRAM device of hynix, model HY57V641620. SDRAM is an array structure, like a two-dimensional table, as shown in Figure 1.
The storage unit can be accessed randomly through row and column addresses. The number of memory rows is 2 ^ 12 = 4096, the number of columns is 2 ^ 8 = 512, and the number of segments is 2 ^ 2 = 4. Its capacity is 4096*512*4=8Mbit.
A [11:0]: Row and column multiplexing addresses. The row address is 12 bits and the column address is 8 bits lower. D[15:0] bidirectional data port. The operation sequence of SDRAM is divided into three parts: initialization, writing and reading. Controller design is based on these three parts of the timing. After the initialization is completed, the read-write operation of the memory can be realized. The initialization sequence is divided into four parts, thermostatic element as shown in Figure 2. Us input delay.
Used to stabilize the state of each part of the circuit. All segments are pre-charged. Precharging means closing an existing row and activating another row. A10 bit, pre-charge all L_BANK, A10 bit, pre-charge fixed L_BANK. A refresh cycle. SDRAM data is stored in capacitors. SDRAM is characterized by periodic refresh and charging capacitors to ensure that data is not lost. The effective storage time of data in capacitor is 64ms, and the device storage unit has 4096 rows.
The refresh time of each row is 64ms/4096 = 15.625us. Mode register settings. By assigning the address bus to configure the mode, it can be used to control the reading and writing mode of the device. The specific contents of the reading and writing modes are listed in Appendix [1]. The system configuration register value is: 000_011_0_111, that is, setting the latent length of 2 clocks, page mode burst reading and writing, sequential transmission mode. After the mode register configuration is completed, the device can read and write normally. Because of the multiplexing of row and column addresses, the row and column addresses cannot be transmitted at the same time. The reading and writing sequence is shown in Figure 4.
When reading data, first send the line address to make the line valid. After Trcd, column addresses and read-write valid signals are sent. Trcd is called row validity time. Since the column address is only 8 bits, the value of [A11. A8] can be assigned to 4’b0000 or 4’b0100.
When the value of A10 is 1, the device is automatically pre-charged. The control signals CKE, CS_N and WE_N should be effective at the same time when sending the column address to read data. When the read command is valid, the data must be magnified before it can be output, which is called Tcl. Tcl is usually 2 to 3 cycles. When writing data, the sequence of row and column addresses is the same as that of reading data. There is no latency time for writing data, but it still takes time for data writing devices, called write-back delay Twr. No pre-charging is allowed during Twr time. The module generates commands such as initialization, refresh, read and write.
Based on the initialization sequence, the order of pre-charging, 8 refresh cycles and mode register settings is generated successively during the stable period of 200us. The init_timer is defined as 16 bits. The size of INIT_PER is defined as 25 000.
/ 125 us * 25000 = 200 us. Then it is the pre-charging of 20 clocks, 8 refresh cycles and register configuration. Define the constant REF_PER size of 1953.
After 15us, the line is refreshed with a total refresh period of 64ms.
If INIT_REQ is valid, an additional 200 clocks are required, and the refresh request is regenerated after initialization is completed. The module translates the commands of reading, writing, pre-charging and refreshing into correct control commands, and connects them to the control pins of SDRAM: CKE, CS_N, RAS_N, WE_N, etc. to make SDRAM perform correct actions. Among them, command_delay and command_d are used for internal delay.
The function description of the module is divided into three parts, as shown in Figure 5. When the input initialization command, charging, refreshing, reading and writing command are valid and the command completion mark is zero, the corresponding internal command is positioned. In order to ensure the effective execution of commands, it is necessary to execute a delay when an internal command is generated. In order to ensure the accuracy of delay, the delay circuit is implemented by shift register. After the shift registers are merged in and out in series, and the command_done is reset after 8 clock delays, the next command can be accepted. The relationship between SDRAM action and input control signal is shown in Table 1. Among them, BTR is a sudden stop operation. When the internal read-write command is valid, first select, that is, activate the operation, and then after the delay Trcd, mark do_rw is valid to perform the read-write operation. The top-level physical circuit is shown in Figure 6. The system sets the page mode control command pm_stop. If pm_stop is valid, the non-page mode requires additional delay. In the system, this controller cooperates with FIFO to complete data access.