A design of DDR2 controller for LCoS sequential color display is presented. The controller is based on AMBA AHB-Lite 3.0 protocol, in order to improve the system bandwidth. This paper analyses the hardware architecture of color-to-chronological color conversion in LCoS space. By storing a frame of RGB data into a bank of SDRAM, and reading RGB data from different positions of bank in turn, the conversion of image data display mode is completed. Then, the stability of the controller system and the correctness of image data conversion are verified by the test of software platform and hardware platform. With the continuous progress of liquid crystal display technology, LCoS (Liquid Crystal on Silicon) technology will become the most potential display technology in the 21st century. LCoS chip is a display driver chip based on silicon-based liquid crystal micro-display technology. It is often used in portable mobile electronic devices. It has the advantages of low power consumption and high resolution. RGB spatial color display is the most commonly used color display mode in LCoS chips at present. It uses the brightness of red, green and blue primary colors to quantitatively represent color, and it is a way of mixing colors by superimposing RGB primary colors. The proportion of the three colors is different, and the color obtained is different. Various mixing effects can be obtained by changing the mixing ratio. Any color is represented by a pixel in the RGB color space.
The disadvantage of RGB space color is that the three components of R, G and B are highly correlated. That is, if a certain component of a pixel changes to a certain extent, the color will probably change. For LCoS sequential color, a complete RGB color image input is first separated into three monochrome fields of RGB, and then written into the LCD screen in turn. At the same time, after each frame of monochrome sub-field valid data is written and LCoS liquid crystal response is completed, the corresponding LED light source is lit, thus completing the sequential display of RGB monochrome images. Only the frame rate is high enough, because of the visual temporary characteristics of the human eye, it feels like a stable color image. Compared with space color display, it has higher resolution and lower power consumption on the same display screen. In order to separate RGB color images into R, G and B monochrome sub-fields, we embedded DDR2 SDRAM (hereinafter referred to as DDR2) controller in LCoS display chip. Off-chip DDR2 plays a very important role as the cache of a single LCoS chip. The controller writes the external input image data into the DDR2 frame, and controls the read address to read out the data from the subfield of red, green and blue frames in DDR2 according to the requirements.
In order to connect DDR2 outside the chip and indirectly control it, we embedded the design of DDR2 controller inside the display chip.
Generate read/write commands and addresses for DDR2 and cache them in FIFOs for DDR2 controllers to call at any time, provided by AHB master. The clock and data signals received by the controller system are given by Mipi interface or RGB interface. Direct control of DDR2, decoding the commands generated by AHB master, generating a series of operations such as read/write/refresh, etc. The various commands issued by DDR2 should meet the specific timing requirements. Initialization of DDR2 must be completed when power is on. Establish data channel between user and DDR2, transfer data needed to be written or read between DDR2 and user interface, and adjust DQS signal timing corresponding to read/write operation to meet the requirements of DDR2. The data read out in DDR2 is cached. Because the speed of direct reading is very high, the data returned directly will exert great pressure on the data processing in the later stage. Therefore, it needs to be cached before it is sent to the subsequent processing. DDR2 controller is mainly composed of five parts: low power switching module, data interface module, register interface module, core module and physical layer module. Fig. 1 is a schematic diagram of the controller, in which the red clock signal (clk_x) is enabled only in scanning chain test (DFT) mode. The code level of DDR2 controller is test logic with scan chain. I/O module leaves several input and output signals of scan_en, scanmode, scanin and scanout. The chip chooses to work in DFT mode or in normal mode.
Through external pin control, these signals are input into different functional modules to realize DFT mode. Now we do not do DFT, we need to connect the external control to a fixed value, so that it always works in the normal mode. That is, at the top of the asic, the above four signals are suspended (normal mode). In high performance SoC (System-on-Chip), dynamic power consumption accounts for the vast majority of the overall power consumption. Clock gating technology is an effective way to reduce the dynamic power consumption of the circuit, and dynamic clock gating technology can achieve lower dynamic power consumption on this basis. When idle state occurs during the operation of the controller, or it needs to be converted to low power mode, the module can switch the working state by setting low power or self-refresh (SR) mode. In general, several clock cycles are needed to enable the controller to switch from the current state to the normal state, and then to the new state. When DFT mode is enabled, the dynamic clock gating module is used to generate the clock signal needed in this mode. The data flow of this module is shown in Figure 2. The data interface module mainly includes AHB master module, AHB slave module and arbitration module. The AHB master module is used to receive and output image data to generate data, address and control signals that meet the timing requirements of AMBA AHB-lite bus protocol. The AHB slave module mainly includes data and command fifo, which is used to receive and store the data, command and address information generated by AHB master, and play the role of buffer and cross-clock domain. The arbitration module uses Round_robin algorithm to arbitrate the command and address data generated by AHB slave, and the result and data after arbitration are synchronously inputted into the core module of the controller. Wide data bits, including 32, 64, 128, 256 and 512 bits. The structure of the module is shown in Figure 3. Register interface module includes register port module and register separation module. Register port module receives configuration information of external I2C and reads out internal register data. Register separation module is divided into high-bit and low-bit address configuration controller Core and internal register of physical layer, respectively. Reader register data can be passed through the register side. Output port. Users can configure the internal registers of the controller according to the application requirements of off-chip DDR2. The specific registers can refer to the data manual provided by the memory manufacturer. The core module of the controller mainly includes user-defined module, command queue module, command and address decoding module, write data channel and read data channel, address shift module, automatic refresh and self-refresh module, bank activation and pre-charging module, state machine module and register module after DDR2 power on. User-defined module: Users can define the address and data bit widths of the controller by configuring the corresponding internal registers according to the address and data bit widths of the DDR2 used, mainly the bit widths of bank address, row address and column address.
Command Queuing Module: The commands and addresses output by data interface module are accompanied by priority and source ID. After user-defined module, they are input to command queuing module. Command queuing module queues commands according to such factors as priority and source ID.
After queuing, the commands are output to the following modules in turn. Command and Address Decoding Module: Command queue module output commands and addresses into the decoding module will be decoded into chip selection, line selection, thermostatic element column selection, write enablement and other signals.
Read and write data channel module: consists of eight deep adjustable synchronous fifo. Because the command queue module has a period of time to process commands, the data channel as a data buffer ensures the synchronization of data and commands and addresses. Address Shift Module: Because the number of banks and capacity of DDR2 provided by vendors are different, we need to control address shift by configuring registers to match the DDR memory provided by vendors. Automatic refresh and self-refresh module: Because DDR2 is a dynamic memory, it must charge potential charge at intervals, that is, refresh charge. DDR2 refresh is divided into automatic refresh mode and self-refresh mode, self-refresh mode is selected in low power state or dormant mode, and automatic refresh mode is selected in normal mode. All banks are refreshed once at 7.8us interval. Bank activation and pre-charging module: when reading and writing data on each line of bank, it is necessary to turn off the previous line and pre-charge it once, so that the capacitor is full of energy to prevent overcurrent. Then, the line activation is carried out to open the lines to be read and written, and then it can read and write.
When all banks are automatically refreshed, it is necessary to turn off all banks for pre-charging. Then the line activates the line to be read and written, and then it can read and write normally.
State Machine Module after power-on: There is an initialization process between DDR2 memory power-on and normal reading and writing data. The specific initialization process can be seen on DDR2 data sheet. The module has a correct state jump process in the initialization process. The register module of the controller: Users can configure the corresponding register parameters in the module according to their needs. The data flow of this module is shown in Figure 4. Physical layer module mainly includes IO module, data channel module and register module. IO module: namely pad module, the data, address, clock and other signals of the controller are output to the off-chip DDR2 through this module. Data Channel Module: The data signal of the controller is divided into high-low bit and double-edge sampling data in this module. At the same time, the DQS signal is output through DLL to sample data more accurately. The read-return data of the memory is also divided into high-low bit and double-edge sampling data. Register module: Users can configure the corresponding register parameters in the module according to their needs. After the functional verification of the software platform, the data returned from off-chip SDRAM reads meets the requirements of sequential color. The controller system has high clock frequency, good stability and low power consumption. The function simulation waveform is shown in Fig. 5. This paper introduces the design and system solution of DDR2 controller used in single-chip LCoS to realize sequential color display. It focuses on the design of controller core and data interface module, and builds a hardware platform for verification. For the conventional 60 Hz color video source, LCoS LCD response time can only be displayed within 3 ms. The system of DDR2 controller adopts 360MHz clock, and the frame refresh rate of 60Hz can only be achieved by using SDRAM with double edges of 800MHz outside the chip. At present, the LCoS chip has been put into production.
At the software level, the results of function test and timing test fully meet the requirements of RGB space color to timing color, and the power consumption is lower.