Twenty-eight series chips of TI company are commonly used in traditional servo controllers. They belong to ASIC chips. The manufacturer has provided some common and fixed peripheral modules for users. Users can not add, delete or modify their functions at will. However, with the emergence of more and more dedicated servo systems, these fixed peripheral resources can no longer meet the needs of servo developers. A servo controller based on SoPC is proposed, which uses the chip of FPGA to customize the required CPU soft core and peripherals. The current loop regulator is hardware-based, and the modules such as ADC and SVPWM are customizable to meet the development needs.
In addition to the advantages of SoPC technology itself, it also achieves functions and performances that can not be achieved by traditional servo control architecture, thermostatic element such as speed sampling and current sampling mean filtering by MT method using hardware. It is proved that the design scheme is feasible and superior to the traditional servo controller architecture in function and performance. At present, SoPC technology has been widely used in many occasions. Its advantages such as short development cycle, flexible design and direct user-oriented are the reasons for its rapid development. FPGA is a way to implement SoPC technology. In this paper, compared with the traditional servo system, using Altera’s FPGA, a design and development scheme of servo controller based on SoPC technology is proposed. In this process, IP cores with independent intellectual property rights are designed and implemented, including IP cores of current loop PI regulation algorithm, SVPWM IP cores, SPI interface current sampling IP cores, MT speed measurement IP cores, etc. Thus, independent intellectual property rights can be more effectively protected. The schematic diagram of the overall design scheme is shown in Fig. 1. Among them, _is the speed instruction. After the speed regulator processing, the current instruction Iq is generated and fed into the current regulator.
Then the direct and [23] transformations are realized through Park? 1 and Clarke? 1 transformations. The results are fed into the SVPWM module to generate the PWM wave, which controls the switching action of the IGBT bridge arm to realize the control of the three-phase current of the motor. In the feedback part, current sampling is realized by ADC module, and the result is transformed by Clarke and Park. The signal of motor encoder is transformed into position information and speed information after receiving by Decoder module, and then into the adjustment and conversion module. In the whole process, except the speed regulation part is implemented by software, the other parts are all implemented by hardware tools such as DSP Builder and Verilog Hardware Description Language, which can effectively increase the frequency of current loop and reduce the CPU burden [2].
In this paper, PI (proportional and integral) regulator is used as current loop regulator. Proportional control is the simplest control method. The output of the controller is proportional to the input error signal. When there is only proportional control, there is steady-state error in the output of the system. In integral control, the output of the controller is proportional to the integral of the input error signal. For an automatic control system, if there is a steady-state error after entering the steady-state, the control system is called a poor system [3]. In order to eliminate the steady-state error, the “integral term” must be introduced into the controller. If the system has steady-state error, the integral term will increase with the increase of time. Even if the error is small, the integral term will increase with the increase of time. It drives the output of the controller to increase and the steady-state error will be further reduced until it equals zero. Therefore, the proportional integral (PI) controller can make the system without steady-state error after entering the steady-state. In this paper, a PI regulator is designed and implemented by using DSP Builder. Its program block diagram is shown in Figure 2. Its input includes instruction cmd, feedback fbk, proportional gain kP and integral gain kI, and its output is pi_out. The program is compiled by DSP Builder to generate VHDL files, and then integrated into Quartus II project to realize the adjustment function. Fig. 3 shows that there are eight kinds of safe vector states in the five-segment space vector synthesis method including dead-zone function. U0 (000) and U7 (111) switch states can not generate effective current in motor drive, so they are called zero vector. The other six vector states are U1 (001), U3 (011), U2 (010), U6 (110), U4 (100), U5 (101). They divide the voltage space of 360 degrees into six sectors of 60 degrees one sector. Using these six basic effective vectors and two zero vectors, any vector within 360 degrees can be synthesized. The logic diagram drawn by DSP Builder is shown in Figure 4. There is a counter of 24B and three comparators. The state of the current counter and comparator is input into the state machine to obtain three logical values of PH1, PH2 and PH3. Then the six-way PWM signal waveforms of SV1, SV1*, SV2*, SV3* are separated by dead-zone processing. The characteristic of this design is that it can modify and adjust the PWM cycle through T3CMP register according to the need of use; if it needs to change from 5-segment PWM to 7-segment PWM, or from center alignment to edge alignment, it is relatively easy to achieve. Because there is no analog circuit in the selected Altera’s FPGA, it is impossible to directly realize current sampling, so an additional current sampling circuit is needed. AD7478 and AD7476 sampling chips of AD company are selected to read current sampling data by SPI interface. The highest 20 MHz SPI transmission clock is selected and the sampling frequency is 1 MHz. In addition, the regulation period of the current loop has been determined to be 10 kHz. Therefore, in order to read the phase current into the regulator more effectively and authentically, 100 uninterrupted sampling can be carried out in a current loop regulation cycle, and then it can be accumulated and the mean value can be obtained, thus the distortion of current sampling value caused by different sampling time points can be minimized.
This scheme requires a large amount of work (100 additions and one division) in a relatively short time (0.1 ms). If the traditional servo controller architecture (such as F2812) is completed by software operation, it will consume a lot of CPU computing resources and lead to its failure to effectively complete the current loop regulation. The Servo Controller based on SoPC uses the logic of the FPGA, which is realized directly by the hardware. It does not occupy CPU resources, and can complete this work reliably and efficiently. Encoder information processing includes two parts: on the one hand, the acquisition of location information; on the other hand, the acquisition of speed information.
Incremental encoder is used here to output three groups of differential square wave signals A, B and Z. When clockwise rotating, A is ahead of B 90 degrees. When counterclockwise rotating, B is ahead of A 90 degrees. Each rotation of encoder produces a square wave signal Z at a fixed position. By using Verilog programming language, the counting of A and B signals after 4 times of frequency is realized, and the direction of rotation is obtained according to the advance relationship between A and B, thus the acquisition of location information is realized. Similarly, Verilog program is compiled to realize the speed acquisition of M method and T method. M method is counting method. The signal of A and B after four times of frequency is counted in a fixed period (1 ms). The speed value is calculated by counting result and fixed period. T method performs timing for the period of A or B signals, and then calculates the velocity from the periodic value of the unit pulse.
The two methods have their own advantages and disadvantages: M method has higher accuracy of acquisition speed when the motor speed is high, and T method has lower accuracy when the motor speed is low, while T method has the opposite effect. When the motor speed is high, the accuracy of acquisition speed is low, and when the motor speed is low, the accuracy of acquisition speed is high [5]. Therefore, MT method can be used to combine the two methods. The velocity value obtained by M method is higher than that obtained by T method when the velocity is lower. The switching point can be determined by the information of sampling clock and counting period. Fig. 5 calculates the accuracy curve of M-method and T-method when speed sampling varies with rotational speed under the condition of 12,000 p/r pulse per revolution, 20 ns sampling clock and 1 ms counting period. The intersection point of M-method and T-method is at 1,118 r/min, which is set as the switching point of MT method. It can be seen that the maximum error occurs at the switching point and is less than 0.5% after using MT method for speed sampling. NIOS II is a user-configurable 32-bit RISC embedded processor using Altera NIOS II as CPU. It is the core of SoPC. The processor is implemented as a soft core with high flexibility and configurability [6].
In addition, it supports the use of special instructions, which are hardware modules added by users, and it adds arithmetic logic unit (ALU). Users can create up to 256 special instructions [7] for each NIOS II processor used in the system, which enables designers to fine-tune the system hardware to meet performance objectives. The special instruction logic is the same as the instruction of NIOS II itself. It can fetch values from up to two source registers and can optionally write the results back to the target register. At the same time, NIOS II series supports more than 60 peripheral options. Developers can choose the right peripherals to obtain the most suitable combination of processors, peripherals and interfaces without paying for silicon chip functions that are not used at all. Therefore, the designer can change the CPU according to the change of system requirements, and choose the best solution to meet the performance and cost, without affecting the existing software input [8]. The components needed to be included in the customized NIOS I I soft core are SDRAM Controller, Timer, JTAG_UART, System ID, Parallel I/O, etc. In addition, we need to add floating-point hardware multiplier and floating-point hardware divider to the customized instructions, so as to ensure that the floating-point operation in the software can be completed in less instruction cycle, improve the efficiency of the calculator and reduce the CPU burden [9]. After efforts, the first prototype has been manufactured according to the scheme. Its current loop bandwidth, current precision, speed precision and other indicators have met the requirements. On this basis, the logic resources and pin resources of the FPGA still have large redundancy space, which is enough to realize more functions such as fieldbus, absolute encoder interface and so on. The selected test motor is the Permanent Magnet Synchronous Motor (PMSM) of 140NYS? L. Its main parameters are rated speed of 3 000 r/p, rated power of 4 kW, rated current of 8 A, etc. Mainly carries on two tests, the plugging test and the on-load test, the test results are as follows. This paper lists the blocking test in the case of current instruction 3A and 8A.
The straight axis current feedback Iq_fbk is shown in Fig. 6. The horizontal axis is time, the unit is 0.1 ms; the vertical axis is current, the unit is 0.01 A.
The overshoot amplitude and the time of oscillation can be adjusted by adjusting the proportional gain and integral gain in the module.
It can be seen from the graph that the current can enter the stable state quickly under the blocking condition, and there is no steady-state error, and the current accuracy is controlled within 5%, which meets the requirements of the servo controller. Fig. 7 (a) is a curve drawn from the Va value of the regulator output during the acceleration of the motor. Fig. 7 (b) is a curve of the three-phase current of Ia, Ib and Ic collected during the constant speed process. Compared with the traditional servo system under the same test conditions, the smoothness and authenticity are greatly improved. It is concluded that the design scheme of the servo controller based on SoPC is feasible, and has better flexibility and adaptability than the traditional ASIC scheme. It has surpassed many functions and performances, such as current sampling accuracy, current loop regulation efficiency and so on. On the other hand, the core function modules such as SVPWM and PI regulator developed independently in the R&D process are effectively preserved in the form of IP core, so they can protect the independent intellectual property more effectively, so this scheme has a good application prospect.