When the speed of an aircraft engine exceeds the set value, it needs oil cutting control, which is of high importance on the aircraft.
This paper provides a design scheme to improve the reliability of the controller. Under the condition that the basic reliability changes little, the anti-interference ability of the product can be improved by using dual-channel detection design, so that the output of the controller can be more stable and reliable, and the engine parking accident can be avoided by misoperation. The design is applicable to the aircraft engine control system and the control system which needs to improve the anti-jamming ability. In the field of aerospace control, it has a relatively wide range of applications. Speed limit controller is the control device of an aircraft engine overspeed protection system. The input signal is taken from a magnetic speed sensor proportional to the engine speed. When the engine turbine speed exceeds the specified value, the controller drives the overspeed device to cut off the fuel supply to protect the engine from being damaged by overspeed.
Based on the importance of the product in the system, reliability design is put in the first place in the design to ensure that the controller will not stop the engine because of the interference signal or the failure of some devices.
The speed limit controller is composed of two independent and identical channels and a state information management module which is monitored by microprocessor. Only when the two channels get the overspeed signal at the same time can the cut-off signal of fuel supply be generated, which can effectively avoid misoperation. At the same time, the state information management module completes the monitoring of input/output state under the control of software. It can also communicate with the host computer through RS-232 bus, monitor the current status information and acquire important recording tasks. Signal conditioning and control module I and signal conditioning and control module II have the same principle and working mode. The signal conditioning and control module compares the speed signal conditioned with the set speed, and outputs the overspeed control signal when the overspeed condition is satisfied. When module I and module II output the overspeed signal at the same time, the speed overspeed is determined, thermostatic element the overspeed signal is output, and the fuel supply of the engine is cut off. The power module provides all kinds of power supply needed in the product. When the signal discrimination and status information management module realizes the failure of the product output overspeed signal, the related information and various signals are stored and then invoked by the host computer. Through fault data analysis, ground crew can determine the cause of system failure and effectively improve maintenance performance. The controller block diagram is shown in Figure 1. The speed limit controller consists of detection channel I, channel II, management module and power module.
Its working principle is shown in Figure 2. The principle of two independent channels detection (channel I and channel II) of speed limit controller. Each detection channel includes speed signal acquisition and processing circuit, logic processing circuit (signal discrimination and control circuit), driving circuit and so on.
Speed signal acquisition and processing circuit: F1 frequency signal is processed by limiting amplitude and anti-audio interference. The processed frequency signal is filtered and amplified into square wave conversion circuit, amplitude detection circuit, and then input into CPLD for logic operation. Logic Processing Circuit: CPLD counts the frequency signal and compares it with the set frequency. CPLD processes various input discrete variables and outputs control signals through logic processing. Maintain the data exchange with the CPU in the management module, and transmit all kinds of state data to the management module for processing.
Driving circuit: The overspeed control signal is amplified by the driving control circuit to drive the overspeed relay. CPU reads CPLD data and other control states in channel I and channel II and stores them in non-volatile memory.
It communicates with PC through RS-232, and downloads data in non-volatile memory during maintenance. The input power of 28V is entered into surge suppression module after filtering module. After processing, the input DC/DC module forms stable ( 15V, 5V) DC power supply, which is supplied to different circuits.
The speed limit controller software resides in the CPU memory of the state information management module.
It mainly completes the input/output state monitoring of the product. It periodically collects the speed amplitude and frequency of detection channel I and detection channel II. At the same time, it periodically reads the data/state of CPLD in detection channel I and detection channel II (including speed frequency, working state, speed signal amplitude) through data bus. The data/state of the non-volatile memory is stored when the fault occurs; the data/state of the amplifier is continuously read when communicating with the external monitoring equipment through RS-232 bus, and the data/state of the non-volatile memory can be read out when the condition monitoring is maintained. The software has the functions of power-on self-check and periodic self-check. Power-on self-check includes RAM self-check, XRAM self-check inside CPU and non-volatile memory self-check. Periodic self-check mainly checks reference voltage of A/D converter. The functional module structure of the software is shown in Figure 3. When the overspeed control signal read from the detection channel I CPLD does not match the overspeed signal of the detection channel I. When the overspeed control signal read from the detection channel II CPLD does not match the overspeed signal of the detection channel I. Speed and frequency data and various state data in CPLD. Fault data can be stored in non-volatile memory, which can record 16 groups of data/states, and cyclically cover the storage from low address space to high address space.
I2C bus communication interface is used between communication monitoring software and non-volatile memory.
When channel I or channel II sends out overspeed control signals, yellow indicator lights are used in the cockpit to warn maintenance personnel that the speed limit controller is out of order and needs to be repaired. When channel I and channel II both send out overspeed control signals, the overspeed relay action sends out the cut-off signal of fuel supply. The management module stores and uploads the relevant data to the host computer in case of failure, which improves the product’s testability and maintainability. In this paper, a dual-channel design is proposed to make the single input signal output control signal after two detection, which effectively improves the anti-interference ability, makes the output overspeed signal more credible, avoids the abnormal output of a single channel leading to engine parking, and meets the requirements of aircraft flight safety.