To solve the testing and debugging problems of complex chips, a boundary scan controller supporting the IEEE 1149.7 standard is proposed. Based on the in-depth study of the IEEE 1149.7 standard and boundary scan test technology, the boundary scan test controller supporting the IEEE1149.7 standard is successfully designed by using the upper computer to program software and developing IP core through Quartus II platform. The experimental results show that the controller can generate two-line star signal and four-line output signal in accordance with the standard of IEEE 1149.
7. The standard of IE 1149.1 has played an important role in testing and fault diagnosis of integrated circuits since it was put forward in the 1980s. However, with the intensification of chip integration, traditional testing methods can not meet the requirements of testing and debugging at this stage.
In this case, the Testability Bus Standards Committee unanimously voted in 2009 to adopt the IEEE 1149.7 standard, which is compatible with all the functions specified in the IEEE 1149.1, and adds new functions, providing a new dual-pin testing and debugging method [1?2]. Based on the research of the standard of IE 1149.7, the IP core of the controller designed in document [2] has only been simulated, but has not been simulated and downloaded to the actual FPGA chip. The main functions of document [3] and document [4] are to realize the functional level simulation of two-line star scan of the standard of IE 1149.7, and the verification of the actual circuit and the upper level are not carried out. Computer software research.
At present, most of the test controllers conforming to the standard of IEEE 1149.7 are still at the simulation level, without considering the signal delay in the actual circuit. So the boundary scan controller based on the actual circuit board designed in this paper has made great progress in technology, and has very important practical significance for its further development. The so-called ZBS (Zero? Bit Scan) refers to a DR (Data Register) scanning state sequence of the TAP (Test Access Port) controller from the Select? DR state to the end of the Updata? DR state, without the Shift? DR state in the middle. There are two paths for the generation of a complete ZBS, the first one is from the Select? DR state, then through the Capture? DR, Exit1? DR state, and finally to the Update? DR state; the other is from the Select? DR state, then through the Capture? DR, Exit1? DR, one or more Pause? DR, Exit2? DR, and finally to the Update? DR state. Once the Shift? DR state is passed during the state transition, the control level is locked. When the control level is locked at 2, the TAP. 7 controller command is indicated. Figure 1 shows the 16 state machine of the TAP controller. All state transitions occur at the rising edge of the TCK (Test Clock). The 0 and 1 on the arrow represent the low and high levels of the TMS (Test Mode Select) sampled at the rising edge of the TCK. Of all the 16 states, there are six stable states: Test? Logic? Reset, Run? Test / Idle, Shift? DR, Capture? DR, Shift? IR and Capture? IR.
MScan scanning format is the only scanning format that supports both direct and indirect allocation of TAP controller addresses. MScan scanning format consists of delay unit and scanning data package. The generated load unit has at least six TCKC (Test Clock) signal cycles. For each TAPC (Test Access Port Controller) state, the input/output information flow contains the same information. In Figure 2, the SP (Scan Packet) package in MScan scanning format contains six bits of information. nTDI and TMS represent the information sent by the controller to the target under test. PC0, RDY, PC1 and TDO (Test Data Output) represent the data information read back by the controller from the target under test. The boundary scan controller communicates with the host computer through the USB 2.0 interface. It calls the pre-set test instructions and data in the database through the host computer program and sends them to the controller. The controller generates waveform signals conforming to the standard protocol of IEEE 1149.7 and sends them to the system under test.
At the same time, it inserts the number from the test response of the system under test. The database is convenient for system fault diagnosis. The overall design block diagram is shown in Figure 3. The boundary scan controller unit is constructed by Cypress’s USB conversion chip CY7C68013A? 128AC and JTAG main control chip ACT8990. USB conversion chip converts USB protocol data, realizes communication between host computer and boundary scan controller, converts data sent by host computer into signals recognized by JTAG main control chip, and sends them to the FPGA module after operation through ACT8990, thus generating test signals conforming to the standard of IEEE 1149.7.
While sending test data and instructions downward, the USB conversion chip transmits the test response returned from the system under test to the host computer, which facilitates the subsequent fault diagnosis of the system. Therefore, it plays an important role in the construction of the whole test system. As can be seen from Figure 3, the FPGA module receives the data sent by the boundary scan controller of IEEE 1149.1 through the TDO signal line, configures its registers, and generates test signals conforming to the standard of IEEE 1149.7. When it is a two-line star scan, data is sent to the system under test by TCKC (Test Clock) and TMSC (Test Mode Select) signal lines, and the test response returned is packaged on the TMSC and transmitted to the host computer. When it is a four-line output test, data is sent to the system under test by TDOC (Test Data Output), and the system under test is received by TDIC (Test Input). The test response returned by the system, TCKC and TMSC cooperate to complete the state conversion. All state transitions in the sending and receiving process should conform to the state machine transition mechanism of TAP controller shown in Figure 1. The development of the FPGA module is based on the Quartus II application platform, the design of IP core is based on Verilog language, and the top-down design method is adopted [4,6]. ZBS, MScan, Command and other functional modules are invoked through the top-level module to send control level commands and test data sequentially. Device driver is the communication bridge between host computer and boundary scan controller. Only through this hardware interface can the host computer control the equipment to do the corresponding work. It occupies a very important position in the whole system. The driver of this system is based on WDM (Windows Driver Model), and is developed by DDK (Device Driver Kits). DDK provides the necessary resource files, development technical documents, compiling and connecting programs for the driver development. Device driver mainly includes INF file (Device Information File), firmware download driver. Among them, INF file is a kind of pure text file, which has its own writing rules. Each INF file is written in accordance with these rules. It is a description file of device information, which contains device description information or script information to control device driver installation. When USB device is connected to PC, the system searches all INF file information, and compares it with the interface information or device information of USB device acquired by PC, so as to find the USB device. Prepare the matching INF file, and then install the device driver correctly according to the installation information in the INF file. The function of firmware download driver is to download firmware programs to the internal RAM (Random? Access Memory) of the USB control chip CY7C68013. The firmware download driver used in this system is bulkloader. sys. Its generation process is to convert the user’s firmware program into C file, and then compile it with DDK software development kit. When the boundary scan controller is connected with the host computer, the host computer obtains the installation information in the INF file and loads the firmware download driver. Firmware program is written into EROM (Erasable Read Only Memory) or E2PROM (Electrical Erasable Programmable Read? Only Memory). It is the underlying software of system work, which determines the quality and performance of hardware devices. The firmware programming of CY7C68013 is based on the firmware framework provided by Cypres, which mainly includes two files: fw. C and bulkloop. C. Bulkloop. C file is the core part of firmware program. It mainly includes peripheral device operation function. In this file, add corresponding code to realize peripheral device function. In this system, the main function of firmware program is to parse the data sent by the host computer and send it to the corresponding register of JTAG controller ACT8990. At the same time, the test response is read from the buffer of ACT8990.
The host computer application program is designed and developed based on VC 6.0. It is responsible for extracting test data from the database and sending it to the boundary scan controller. At the same time, it receives the returned response and inserts it into the database. The software flow chart is shown in Figure 4. The application program mainly includes the configuration of ACT8990, the processing of test data, the sending and receiving of data, and the processing of response, among which device IoControl () is used to complete the sending and receiving of data. The boundary scan controller communicates with the host computer through the USB 2.
0 interface, and sends the pre-set data in the database to the controller through the host computer program. According to the received instructions and data, the controller carries on the corresponding operation, generates the test signal conforming to the standard of IEEE 1149.7, and sends it to the system under test. At the same time, the signal generated by the signal Tap II Logic Analyzer sampled controller in Quartus II software is output to the upper computer through USB? Blaster transmission line for analysis and verification. In the two-line star scanning part, taking MScan scanning format as an example, the upper computer sends pre-set test data successively from low to high. The hexadecimal format of the data is as follows: 00 00 00 00 00 00 00 00 00 00 24 02 00 06 00 00 00 00 00 00 00 00 00 00 00 23 00 00 00 00 00 00 00 00 00 00 00 001 1A02. According to the configuration instruction data sent by the host computer, the controller first performs ZBS state loop, and then locks the control level of ZBS state loop twice to 2.
Then it sends STFMT (Store Format) command, chooses MScan scanning format, sends CP (Check Packet) packet on the basis of the instruction sent by the former, and finally transmits and receives SP packet data. 。 As shown in Fig. 5, the controller is in Run? Test / Idle state at T0, and then the value of TMSC is “1010111” at the rising edge of TCKC. According to the state transition diagram, the state is completed through Select? DR, thermostatic element Capture? DR, Exit1? DR, Pause? DR, Exit2? DR, Update? DR, and a ZBS loop is completed. Finally, the state is returned to Select? DR state. The state continues to cycle, and ends at T1. Twice ZBS loops, T2 passes through Shift? DR state, which locks the control level at level 2 and T3 to start sending STFMT commands. CP1 package content is 00011, that is, three times in Shift? DR state, CP2 package content is 10000, 16 times in Shift? DR state, and finally, the content of CP check package is 0000, representing standard protocol to advanced level. At T4, MScan scanning format is selected, and at T5, two-wire transmission (i.e., transmission through TCKC and TMSC) is started. The SP package of MScan scanning format contains six bits of information, nTDI, TMS, PC0, RDY, PC1 and TDO, as shown in Fig. 5. The upper computer sends data in hexadecimal format successively from low bit to high bit: 00 00 00 00 00 00 00 00 00 00 00 00 00 01 E FF 1E DF 1E B0 1 E 921 E 771 E 5B 1E 331 E 1A 00 00 00 00 00 00 00 2A 02 00 00 00 00 00 00 00 00 00 00 00 00 00 1A02; ZBS instruction part and MSCAN two-line scanning part are sampled through SignalTap II Logic Analyzer. Firstly, the ZBS state cycle is carried out. After two ZBS cycles, the state passes through Shift? DR and then the control level is locked to 2. Based on the control level 2 generated by the ZBS instruction, the controller begins to send CIDA (Controller ID Allocate) instructions to the system under test.
After CP1 and CP2 in CIDA are executed, the controller begins to execute CP3. To send a total of 35 bits of CP3. As shown in Fig. 6, according to the timing relationship between TCKC and TMSC, the ZBS cycle is first performed. After completing two ZBS cycles, the control level is locked at T1 and CIDA commands are sent at T2. The CIDA instruction is a three-part command. Its function is to assign a unique TAP.
7 controller to each T3 layer and above.