Aiming at the problem that one control terminal is often used to communicate with multiple devices in engineering application, a multi-serial port controller based on FPGA is designed in this paper. The controller realizes one-to-four multi-serial communication function, assigns a FIFO to each serial port in the controller to cache the received data, sets priority for each device’s serial port, and responds to higher priority serial port requests in the work of the controller. In this paper, the design ideas and methods of each functional module are described in detail, and each functional module has passed the ISim simulation, which verifies the correctness of the design.
In addition to carrying special probes, the special monitoring system for floating at sea also includes temperature sensors, GPS positioning system and Beidou positioning system. These devices need to communicate with the control terminal in order to respond to the command of the control terminal and return the monitoring data.
But it is unreasonable to assign a serial port to each device on the control terminal. In order to improve the system integration and reduce the hardware cost, it is necessary to design a one-to-many serial communication controller. The structure principle of multi-serial port controller is shown in Figure 1. It consists of logic control module and five UARTFIFO modules. The former is used to control the logical connection between the main serial port (UARTFIFO_C) and the other four slave serial port (UARTFIFO_i) modules. The UARTFIFO module is used to control the data receiving and receiving of terminals and equipments. UARTFIFO module is mainly composed of UART serial module and FIFO module, as shown in Figure 2. UART serial module includes baud rate generating unit, sending unit and receiving unit.
FIFO module has 16B FIFO buffer unit [1]. Table 1 lists the pin function tables of UARTFIFO modules. As a master-slave communication system, the main serial port needs to process four data sent from the serial port. In this case, it is easy to appear that the main serial port is sending some data from the serial port, and the other one requests a response from the serial port. In order not to affect the subsequent data transmission and avoid data loss, it is necessary to configure a FIFO for each UART receiving module to cache the data received by the UART receiving module [2]. When the UART receiving module receives a frame of data, rec_read will output a positive pulse, and rec_read signal will be used as the write enabling signal of FIFO. Logic control module consists of sending control unit and receiving control unit. The sending control unit is responsible for the logical control of communication between UARTFIFO_C and a slave serial port (UARTFIFO_i), and the receiving unit is responsible for the logical control of communication between a slave serial port and the main serial port. As a master-slave system, UARTFIFO_C chooses to communicate with a slave serial port (UARTFIFO_i). The command format for sending data is address byte command byte. When UARTFIFO_C receives a frame of data, its pin FULL1 outputs a high level, indicating that there is new data in the FIFO. After the sending control unit reads the first frame of data and translates the address, the data of UARTFIFO_C is sent to the TXDBUF (7:0) end of the corresponding serial port according to the address, and whether the TXDOVER1 from the serial port is a high level is judged, if it is a high level. Enables TXDCMD1 to start the sending module from the serial port. The serial peripheral receives the command sent by the control terminal and responds to the command. It returns the serial data in a predetermined format. The UART serial data input terminal RXD corresponding to the peripheral receives the serial data and processes it. The parallel data and the flag bit re_ready are output.
When UARTFIFO_i receives a frame of data, its pin FULL1 outputs a high level, indicating that there is new data in FIFO, the receiving control unit stores the signal of FULL1, and queries whether the TXDOVER1 of UARTFIFO_C is high level. If it is high level, wait, if it is 0, send an enabling signal RDREQ1, read out the FIFO cached data in UARTFIFO_i and pass it to the TXDBUF (7:0) end of UARTFIFO_C, thermostatic element enabling TXDCMD1 until EMPTY1 in UARTFIFO_i stops at a high level. When multiple UARTFIFO_i simultaneously send data to UARTFIFO_C requests, the logic control module stores the signals of each serial port FULL1, and determines its priority level, giving priority to responding to higher-level serial port requests, and then responding to lower-priority requests. Figure 3 shows the ISim simulation results of UART module. The simulation waveform shows that the serial data received by the serial port RXD end outputs a positive pulse from rec_buf (7:0) while rec_read outputs. When there is data to be sent in txd_buf (7:0), txd_cmd gives a positive pulse to enable serial port sending module. The data is output serially from the TXD end, and txd_over outputs a high level after data transmission. The outstanding advantage of this design is that it can flexibly customize the number of serial ports to meet the needs of multi-serial ports.
It can replace the traditional design method of special serial chips, reduce the complexity of multi-serial system and improve the stability of the system.