With the continuous development of Raschel piezoelectric jacquard warp knitting machine in the direction of multi-bar, large pattern and multi-needle bed, the traditional industrial field bus represented by CAN bus can not meet the real-time pattern data transmission requirements of warp knitting machine. In view of this, this paper designs a piezoelectric jacquard control system based on FPGA for GTP optical fiber data transmission. The high-speed GTP interface of XC5VLX50T18 of Xilinx Virtex-5 series is used to realize the high-speed data transmission. When the warp knitting machine is running, according to the trigger signal of the spindle, the pattern information of the corresponding position is transmitted to the piezoelectric jacquard driver by the optical fiber transceiver module. Experiments show that the transmission rate of the FPGA jacquard controller can work at the rate of 6K trigger frequency and raise the speed of the current RD6 model from 850 rpm to about 3000rpm. Therefore, the control system has good application prospects.
At present, with the design and application of new materials and new mechanical parts of warp knitting machine, jacquard warp knitting machine is developing toward high speed and small size.
In order to adapt to the increase of spindle speed and electronic transverse speed, the real-time transmission rate of jacquard control data must be improved correspondingly with the speed of mechanical spindle, which is newly introduced by Karmeyer Company. Trico HKS2-3 series double needle bed Raschel warp knitting machine for example, its electronic transverse motor 3000r/min, A, B needle bed has 120 jacquard combs, a total of 3840 yarn guide needles, electronic transverse movement per cycle of four jacquard send trigger state calculation, the average jacquard every 5 milliseconds must send 480 bytes of process data, with the current jacquard controller single chip computer. RS485 bus speed (maximum baud rate 115200) can not meet the requirements. In addition, with the development of process editing software, the capacity of process pattern data files sometimes reaches tens of megabytes. If the speed of CAN bus 1Mb/S also needs to be uploaded for several minutes, in view of the current speed matching of the whole machine, this paper uses Xilinx Virtex-5 series. Field-Programmable Gate Array with GTP module replaces AVR ATmega128 [2] or C8051F series of mainstream microcontrollers of current jacquard controller. In Verilog language programming, the functions of serial command receiving and parsing, file reading and optical fiber transmission, spindle level jump detection are realized. Figure 1 shows the overall structure of the system. The system interacts with the trigger signal of the serial port of the upper computer and the spindle of the warp-knitting machine in the form of finite state machine. The system is initially initialized as a standby state. After receiving the command of the serial port of the upper computer to start, the system enters the jacket start state. Because there are four trigger signals of the spindle in each bar of the double needle-bed jacket machine to control the jacket needle swing, thermostatic element and these four contacts The signal is triggered by four stroke switches 90 degrees apart and input to the two pins of the FPGA through the optocoupler. After the system enters the jack start-up state, the sequence number of the trigger state of the spindle is distinguished by detecting the level jump of the two pins, and the corresponding jack pattern data is read in the RAM area of the FPGA, and sent to the GTP transceiver that comes with it.
The optical signal is converted to optical signal through Agilent multimode optical fiber transceiver module, which is transmitted to the receiving end through high-speed optical fiber communication line. The pattern information of this bar is received through the GTP interface of the receiving end FPGA, and the number of shifting registers of the receiving end FPGA is invoked by interrupt trigger mechanism. The jacquard needle is driven by the jacquard driving circuit to swing according to the removed data. Thus, the transfer of process pattern data is completed. The jacquard control system of warp knitting machine is designed by using XC5VLX50T18[3] FPGA of Xilinx Company as the main control chip. The main work of the main control chip is to control the whole circuit and provide high-speed GTP interface to realize the conversion of process pattern data and control instructions to high-speed serial data. Modular optical fibers are used to transmit to the jacquard driver circuit. XC5VLX50T contains 3600 ARRAY (row * column), 7200 Slices, 48 DSP48E slices, 480KB distributed RAM and 2160KB block RAM, which are enough to store large pattern files. In addition, XC5VLX50T has 12 channels of RocketIO GTP transceivers and can run at a rate of 3.75Gb/s. In this design, the GTP transceiver at the transmitter mainly converts the process pattern data or control instructions into high-speed serial data and outputs them to the optical transceiver module. The GTP transceiver at the receiving end moves the received data serial to the jacquard driver circuit at high speed. In order to meet the requirement of jacquard driving transmission rate in technical specifications. The optical transceiver module uses Agilent multimode optical fiber transceiver module HFBR-5710LP with a transmission distance of 550m and a working wavelength of 850nm. The working voltage is 3.3v, which can be directly connected with CML driver of GTP module of FPGA. The transmission rate is 1.25 Gbps, which meets the current design requirements. Although the data transmission of the system is accomplished by high-speed optical fibers, the switching between the working states of the system and the receiving of pattern data are still controlled by the command from the host computer. So the system realizes a serial port receiving and sending module [4] in the bottom of the hardware of the FPGA to complete the interaction with the host computer. The module is composed of level detection module, baud calibration and timing module and receiving control module.
The level detection module is used to detect the descending edge of the starting bit level of the serial line, and then a high pulse is generated by H2L_Sig to the receiving control module to indicate the beginning of the receiving work. The RX_En_Sig is raised to make the receiving module work, the receiving control module is raised to Count_Sig, and the baud rate timing module is generated by BPS_CLK to the receiving control module. Timing, the receiving module collects data from RX_Pin_In according to the delay time of half bit. When a frame of data is received, a high pulse will be generated to RX_Done_Sig to inform the top-level state machine to parse the data frame. The jacquard driving circuit [2] is shown in Fig. 3. According to the working principle of jacquard yarn guide needle, the driving circuit should add positive or negative 70 DC voltage jacquard needle to piezoelectric ceramics to complete swing in different directions according to the process data. The specific driving process is that the jacquard swing control signal is synchronously and parallel moved from the synchronous data output terminal of the shift register 74HC595 to the DIN pin, then divided into two signals, one input to the positive power switch circuit composed of QA1 and QA 3, and the other input to the negative power switch circuit composed of QA 2 and QA 4 through 74HC541 buffer. The two sets of switching circuits are controlled by DIN.
When DIN is high level, QA1 and QA 3 turn on, QA2 and QA4 cut off, positive 70V voltage output drive circuit output terminal (VOUT); when DIN is low, QA1 and QA3 cut off, QA2 and QA4 turn on, negative 70V voltage output to drive circuit output terminal (VOUT). Because of the driving voltage 70V and the driving current (about tens of milliamperes), the driving circuit chooses MJ11016 (NPN) and MJ11015 (PNP) triodes (withstanding 140 V, rated power 250W). The empirical calculation shows that each triode can meet the requirements of the maximum driving voltage in this circuit. The system uses finite state machine to realize human-computer interaction with the host computer, receiving, saving, reading, sending and transmitting fancy files. Under Verilog HDL programming, the data sent by the host computer is received by serial bus, and stored in the RAM area of the FPGA sequentially. The trigger signal of the spindle is sent to the PLC by the spindle encoder under the start-up working condition, and then transformed to the high and low level signal by the PLC and transmitted to the FPGA by the optocoupler. Under the control of the TTL level signal, the FPGA reads the pattern data of the corresponding spindle signal horizon from the RAM area in sequence, and converts to the high-speed serial number by the GTP transceiver with it. Data is sent to the optical fiber receiving module to complete the electro-optical conversion. The process of data processing at the optical receiving end is roughly the opposite to that at the sending end. After receiving the fixed number of bytes of data, the serial shift register is started to move the data out, and the latch output power of all 74HC595 is increased after the data shift is completed, and the control signal is synchronously output to the jacquard driver. Active circuit. The task of serial communication is to receive the data and commands sent by the host computer and parse them to complete the corresponding functions. Based on the serial port transceiver module mentioned above, this module uses state machine to realize command parsing. The core of this module is to distinguish whether the received data is process data or control instructions. The design of state machine includes three main states: detection of frame head, data receiving and detection of frame tail, and parsing command. In the parsing command state, different branch states are entered according to different commands. The whole command parsing state diagram is shown in Figure 4. After power-on, the state machine is in the frame head detection state.
If the frame head is detected, it enters the receiving and saving data state and automatically switches to the detection frame end state. Otherwise, the state machine is still in the detection frame head. After receiving the data and counting the number of bytes, if the end of the frame is detected, the analytic byte number N state is entered. If N exceeds one byte number, which indicates that the frame is process data, the received data should be stored in the RAM area of the FPGA. If there is only one byte, this frame is the control instruction frame. The control instruction will be parsed and the value of the jacquard control state machine will be modified after identifying the corresponding control command. Finally, return to the detection frame header status, wait for the next command, so cycle. The RX_Done_Sig signal generated by CLK is the reset signal, rst_n is the reset signal, A is the current byte data received by the serial port, current_state is the current state, next_state is the next state, and S0-S2 is the three main state values. Among them, S0 detects the header state, S1 receives and detects the tail state, S2 is the command parsing state, so that the S2 state can be unconditionally transferred to S0 state to re-detect the header at the next clock (when the serial port receives the next byte) after the action output. The value of a above represents the frame header 02H and the frame tail 03H, so when 02H or 03H occurs in the middle of the data frame, it must be escaped to 1BH, E7H and 1BH, E8H respectively, while the escaped 1BH itself must be converted to 1BH, 00H, so that no frame header 02H and frame tail 03H will appear in the data body after processing, which is beneficial to the data frame. Judgment. In Verilog data parsing at the receiving end, if statement can be used to judge whether the escape character 1BH appears in the data body, and then the value before the escape can be restored according to the subsequent value, so that the recovery of the data body can be completed. The above part solves the problems of serial data receiving and command parsing. This part mainly solves the problems of state transition, timing coordination and synchronization after command parsing, such as Jacka start, stop and bar data sending. The specific state transition relationship is shown in Figure 5.
The design of jacquard control state machine includes six states: jacquard standby state, jacquard start state, data state of sending the first part of the bar, data state of sending the second part of the bar, data state of sending the third part of the bar, and data state of sending the fourth part of the bar. By default, the state machine is on Jaka standby. If you receive the signal of serial command startup, it enters the startup Jack state. Otherwise, the state machine is always on standby. After entering the jacquard startup state, any jump in the position of the spindle stroke switch triggers the transfer of the four-step state of the horizontal transmission.
It should be noted here that if the state machine is in the data state of the first part of the sending column, it can only wait to receive the main axis to “01” stroke switch signal, that is, if it receives the main axis to “01” stroke switch signal other than “01”, it will discard, and continue to wait until it receives the main axis to “01” stroke switch signal before entering the next state. State. The data status of other sending columns is similar.
And in this cycle. Any state other than the initial Jacka standby state will enter the standby state as soon as the serial stop command is received. In Verilog implementation, read RAM arrays and send them to GTP FIFO buffers can be encapsulated separately in a process with a loop body. The triggering condition of the process is in the above state.