The hardware connection of LED dot matrix display module, the initialization and working schedule of MAX7219 are introduced. The clock frequency division, data storage and invocation, and the design of MAX7219 controller are realized by programming in VHDL language. The Basys2 development board is connected with the lattice module, and the program is downloaded to the FPGA. The display of 8 x 8 array is realized, which verifies the correctness of the design. The design has practical application value. LED dot matrix display system can not only display characters and images statically, but also dynamically display text, animation, video and other information.
It is widely used in advertising, information dissemination, sports, industry and other fields. There are many kinds of LED lattice display controllers, including MCU [1], ARM [2, 3], FPGA [4], and so on. This paper adopts DIGILENT’s Basys2 portable development board, which is a complete ready-to-use hardware system. It is suitable for circuit design from basic logic devices to complex controllers. Xilinx Spartan-3E series of FPGA devices are embedded on it. There are 16 pins in the 8-point array. If the pin resources are too much to connect directly with the microprocessor, decoders and serial-to-parallel conversion chips are used to control the lattice. The 8*8 array module used in this paper is driven by a MAX7219 chip. Figure 1 shows the main pins of the MAX7219 chip. It has only three input terminals, DIN, CS and CLK, which can be connected to all general purpose microprocessors. Therefore, the 8*8 matrix module driven by MAX7219 overcomes the problem of excessive pins in the dot matrix. The output terminals of MAX7219 chip DIG0-DIG7 are connected to 8*8 matrix H1-H8 rows, and SEG DP and SEG A-G are connected to 8*8 matrix L1-L8 rows.
DOUT can be used as serial output for cascade expansion. MAX7219 contains BCD encoder (not used in this paper), multi-channel scanning loop (automatic polling scanning at a frequency not less than 800Hz for DIG0-DIG7), segment driver (driving SEG DP, SEG A-G8) and 8*8 SRAM (for data storage). The serial 16-bit data is input at the DIN end, and the data contains the information shown in Table 1. The registers of MAX7219 chip are divided into control registers and data registers. There are five control registers: decoding mode, brightness, scan limit, power-off and display detection. The register addresses are 9, A, B, C and F in turn. All possible settings for initialization of each register are detailed in MAX7219 document [6]. The initialization settings of this design are as follows: 0900, decoding mode is set as non-decoding, thermostatic element 8 bits of data in data memory are directly output to 8 columns of 8*8 array; 0 08, set as medium brightness; 0 B07, set the scanning limit as 8 rows, poll 8 rows of 8*8 array; 0 C01, set as normal working mode, no power failure; 0 F00, set as normal working mode, turn off display and check. Measurement.
The data register is implemented by 8*8 SRAM on chip. Register addresses range from 1 to 8, corresponding to DIG 0-DIG 7 pins of MAX7219 chip and H 1-H 8 rows of 8*8 array. The data width of SRAM is 8, in which the stored data values correspond to SEG DP, SEG A-SEG pins of MAX7219 chip and L1-L8 columns of 8*8 array.
The data value stored in the address nH is the information to be displayed in line n of the 8 x 8 matrix. The ctrl_addr Module shown in Figure 2 is used to generate the address addr required by the romip module, so that the addr is self-added 1 (as shown in Figure 3). According to the address, 13 16-bit parallel data douts are extracted from the romip module and input to the MAX7219 controller module.
As shown in Figure 4, when the data latch signal CS is low, the data D15-D0 inputted from DIN are moved into the internal 16-bit register successively along the CLK rising edge of each clock. After continuously inputting 16 bits of data, at the rising edge of CS, according to the D11-D8 address of these 16 bits of data, the value of D7-D0 bits is locked into the corresponding control register or data register. In order to make MAX7219 work properly, we need to write the control program ctrl_dot.vhd of MAX7219 in VHDL language according to the working sequence shown in Fig.
4. Fig. 5 is the input and output port information of MAX7219. The ctrl_dot module realizes the conversion of 16 bit parallel data (15:0) to serial data at each rising edge of the input clock clk, and generates the data latch signal load_cs and clock signal clk_max7219 required by MAX7219 chip, which are connected with the DIN, CS and CLK terminals of the 8*8 array module respectively, and controls the display of the 8*8 array module. The main program segments programmed with if statement and their interpretation are as follows. When loadcs_tmp is 1, make clk_max7219 0; when it detects that the input value data is different from the original data_cmp, update data_cmp (preparing data for next comparison) and data_tmp (loading new data) with data value; make loadcs_tmp 0, shift_f of shift flag bit 1, allowing data shift.
When the data is the same as data_cmp, it indicates that the data is not updated, and loadcs_tmp is 1, and keeps in state to continue to detect whether the data is updated. When loadcs_tmp is 0 and shift_f is 1, the highest bit of data_tmp is output to din, and the other bits are moved one bit to the left to realize the bit-by-bit left-shifting serial output of 16-bit parallel data_tmp, with the clk_max7219 being 0 and shift_f being 0. When loadcs_tmp is 0 and shift_f is 0, clk_max7219 is changed from 0 to 1, and a clk_max7219 clock is generated for every bit of din. When CNT < 15, 16 bits of data are not transmitted, CNT adds 1 to make shift_f 1, and returns to continue serial output along the rising edge of the next CLK clock. When CNT = 15, it shows that all 16 bits of data are output serially, so that CNT is cleared and shift_f is 0. Loads cs_tmp is changed from 0 to 1, which generates the rising edge of data latch signal, latches data, and returns to the next CLK clock rising edge to detect whether the data is updated or not. Clock frequency division module clkdiv_50M divides the 50MHz clock provided by Basy2 development board. It is necessary to ensure that the clock clk_16data provided to ctrl_dot matches the clock clk_rom provided to ROM IP core. Only when all 16 bits of data in ctrl_dot are output serially, can update data be allowed. By analyzing the ctrl_dot.vhd program, we can see that 16-bit data transmission requires at least 34 clk_16data cycles, so the clock frequency of clk_16data must be higher than 34 times the clock frequency of clk_rom. Connect the clock frequency division module clkdiv_50M, ROM address module ctrl_addr, ROM IP core romip and MAX7219 driver module ctrl_dot. After adding pin constraint file, synthesize, implement and generate programmable file.
Download it to Basys2 development board, and show the effect as shown in Figure 7. This paper mainly introduces the VHDL program design of MAX7219 controller. The register address, initialization settings and dot matrix information of MAX7219 are composed of 16 bits of data which are stored in the ROM IP core. Then the serial output of 16 bits of parallel data is realized by programming with if nested statement, thus controlling the dot matrix display of LED driven by MAX7219. In this paper, a large amount of data is stored in ROM to improve the efficiency of programming. In addition, an 8 *8 array module needs only one MAX7219 chip, which is more practical and has a wider application value than the combination driver of decoder and 74HC595 in terms of software programming and hardware implementation.